SN54120
Abstract: SN74120
Text: TTL TYPES SN54120, SN74120 DUAL PULSE SYNCHRONIZERS/DRIVERS MSI B U L L E T I N N O . D L -S 7 2 1 1 8 3 7 , S E P T E M B E R 1 9 7 1 — R E V IS E D D E C E M B E R 1 9 7 2 S N S 41 2 0 . . . J OR W PACKAGE Generates Either a Single Pulse or Train of Pulses
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SN54120,
SN74120
SN741PUISE
SN54120
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Untitled
Abstract: No abstract text available
Text: SN54120, SN74120 DUAL PULSE SYNCHRONIZERS/DRIVERS SEPTEMBER 1971 - REVISEO M A R C H 1 9 8 8 SN54120 . . . J PACKAGE Generates Either a Single Pulse or Train of Pulses Synchronized with Control Functions SN74120 . . . N PACKAGE {T O P V IE W Ideal for Implementing Sync-Control Circuits
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SN54120,
SN74120
SN54120
SN74120
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Untitled
Abstract: No abstract text available
Text: CDCM7005 www.ti.com SCAS793B – JUNE 2005 – REVISED OCTOBER 2005 3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER GND GND GND GND GND GND C VBB GND AVCC AVCC AVCC AVCC AVCC GND STATUS_ REF or PRI_SEC_ CLK STATUS_ D VCXO_IN GND GND GND GND GND
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CDCM7005
SCAS793B
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C28H
Abstract: TS301
Text: 4 ^ ?< ?, SSI 532 Sumsiishiu' Data Synchronizer/ 2,7 RLL ENDEC INNOVATORS IN^INTEGRATION Preliminary Data February 1987 DESCRIPTION FEATURES The SSI 532 Data Synchronizer / 2, 7 RLL END EC provides data recovery and data encoding for storage systems which employ a 2, 7 RLL encoding
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28-Pin
532-C28H
532C28P
C28H
TS301
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32D5362
Abstract: 32D535 32D5321 5351A 32D532 SC111
Text: Data Synchronizer Family Application Notes S SI 32D5321/5322 SSI 32D 535/5351 S SI 32D5362 R E F E R E N C E O S C IL L A T O R An internal reference oscillator generates the standby reference for the PLL. For the 32D5321/5322 and the 32D535/5351, a series resonant crystal of twice the data rate should be used between XTAL1 and XTAL2. For
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32D5321/5322
32D5362
32D535/5351,
32D5362,
32D5362
32D535
32D5321
5351A
32D532
SC111
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X-TAL reference
Abstract: ra7d
Text: SSI 32D539 ¿ m m s y s b m s Data Synchronizer & 1,7 RLL ENDEC ' A TDK G rou p /C o m pany Preliminary Data December 1991 DESCRIPTION Fast a c q u is itio n phase locked lo o p w ith zero The circuit is intended to be used as a data/clock recovery circuit for 1, 7 RLL code in hard disk drive
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32D539
44-pin
X-TAL reference
ra7d
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CDCM7005HFG-V
Abstract: smd y1a
Text: CDCM7005-SP www.ti.com . SGLS390A – JULY 2009 – REVISED AUGUST 2009 3.3-V HIGH PERFORMANCE RAD-TOLERANT CLASS V, CLOCK SYNCHRONIZER AND
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CDCM7005-SP
SGLS390A
CDCM7005HFG-V
smd y1a
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Untitled
Abstract: No abstract text available
Text: AV9170 Integrated •i fCircuit i m n ’i Systems, Inc. Clock Synchronizer and Multiplier General Description Features The AV9170 generates an output clock which is synchronized to a given continuous input clock with zero delay ±lns at 5V Vdd - Using ICS’s proprietary phase-locked loop (PLL) ana
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AV9170
AV9170
AV9170-xxCN8
AV9170-xxCS8
AV9170-01
AV70-1
AV9170-02
AV70-2.
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8x16x16
Abstract: No abstract text available
Text: TRF4903 SINGLEĆCHIP MULTIBAND RF TRANSMITTER SWRS023B − MAY 2004 − REVISED MARCH 2005 D Single-Chip RF Transmitter for 315-MHz, D D D D D D D Programmable Brownout Detector D Integrated Data Bit Synchronizer and Baud 433-MHz, 868-MHz, and 915-MHz Industrial,
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TRF4903
SWRS023B
315-MHz,
433-MHz,
868-MHz,
915-MHz
24-Pin
8x16x16
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Untitled
Abstract: No abstract text available
Text: SY58052AU Ultra-Precision CML Data and Clock Synchronizer with Internal Input and Output Termination Precision Edge General Description The SY58052AU is an ultra-fast, precision, low jitter datato-clock synchronizer with a guaranteed maximum data throughput of 10.7Gbps and a maximum clock of 10.7GHz.
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SY58052AU
SY58052AU
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LVDS register
Abstract: No abstract text available
Text: CDCE72010 SCAS858C – JUNE 2008 – REVISED JANUARY 2012 www.ti.com Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor Check for Samples: CDCE72010 FEATURES 1 • • • • • • • • • • • • • • High Performance LVPECL, LVDS, LVCMOS
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CDCE72010
SCAS858C
500MHz
250MHz)
800MHz
250MHz
LVDS register
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LP3933
Abstract: LP3936 LP3950 LP3950SL LP3950SLX
Text: LP3950 Color LED Driver with Audio Synchronizer General Description Features The LP3950 is a color LED driver with a built-in audio synchronization feature for any analog audio input such as polyphonic ring tones and MP3 music. LEDs can be synchronized to an audio signal with two methods - amplitude
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LP3950
LP3950
CSP-9-111C2)
CSP-9-111S2)
CSP-9-111S2.
LP3933
LP3936
LP3950SL
LP3950SLX
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ZL30142GGG2
Abstract: ZL30142 GR-1244 GR-253
Text: ZL30142 SyncE SONET/SDH G.8262/Stratum 3 System Synchronizer Short Form Data Sheet February 2009 Features • Supports the requirements of ITU-T G.8262 for synchronous Ethernet Equipment slave Clocks EEC option 1 and 2 • Supports the requirements of Telcordia GR-1244
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ZL30142
8262/Stratum
GR-1244
GR-253,
OC-48/STM-16
ZL30142GGG
ZL30142GGG2
ZL30142
GR-1244
GR-253
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ZL30321
Abstract: ZL30116 GPON ONT ONU H1-LOCK GR-253 ZL30121 ZL30130 ZL30138 ZL30321GGG "network interface cards"
Text: ZL30321 GbE/SONET/SDH/PDH Network Interface Synchronizer Short Form Data Sheet February 2008 Features • Ordering Information Provides synchronous clocks for network interface cards that support synchronous Ethernet SyncE in addition to telecom interfaces (e.g. T1/E1,
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ZL30321
ZL30321GGG
ZL30321GGG2
ZL30116,
ZL30321
ZL30116
GPON ONT ONU
H1-LOCK
GR-253
ZL30121
ZL30130
ZL30138
ZL30321GGG
"network interface cards"
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HD15303
Abstract: No abstract text available
Text: HD 153035F 56-Mbps Data Channel Processor # H ITA CH I _ Under Development Description The HD153035F is a 56 Mbps 1-7 ENDEC data separator with built-in read pulse detector, active filter, frequency synthesizer and synchronizer developed for use in magnetic disk drives.
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153035F
56-Mbps
HD153035F
56Mbps.
84MHuctor
HD15303
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siemens Logo 230 rc manual
Abstract: GR-1244-CORE MT9044 MT9044AL MT9044AP TR62411
Text: MT9044 T1/E1/OC3 System Synchronizer Data Sheet Features November 2003 • Supports AT&T TR62411 and Bellcore GR-1244CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces
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MT9044
TR62411
GR-1244CORE
MT9044AP
MT9044AL
544MHz,
048MHz
siemens Logo 230 rc manual
GR-1244-CORE
MT9044
MT9044AL
MT9044AP
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SY02-MFTC
Abstract: 33172 regenerator Crystal 10mhz RALTRON
Text: SYNCHRONOUS EQUIPMENT LOW IN/OUTPUT FREQUENCY CLOCK REGENERATOR LVPECL/LVCMOS OUTPUT SY02-MFTC Date: January 7,2004 SY02-MFTC • INTRODUCTION The SY02-MFTC is a high frequency crystal-based PLL synchronizer designed as a module level subsystem for easy incorporation into telecommunication equipment
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SY02-MFTC
SY02-MFTC
76MHz
33172
regenerator
Crystal 10mhz RALTRON
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endat
Abstract: 7301A
Text: VM7301 VTC Inc. ZDR DATA SEPARATOR / SYNTHESIZER / ENCODER-DECODER WITH WRITE PRECOMPENSATION V a lu e th e C u s to m e r PRELIMINARY FEA TU R ES Data Synchronizer 1,7 Encoder/Decoder Frequency Synthesizer Write Precompensation 3 - 24 Mbits/sec Data Rate
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VM7301
VM7401
44-lead
48-lead
VM7301
endat
7301A
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Untitled
Abstract: No abstract text available
Text: SYNCHRONOUS EQUIPMENT HIGH FREQUENCY CLOCK/SYNCHRONIZER - SY0002B SY0002B Date: June 15, 2001 PRELIMINARY • INTRODUCTION The SY0002B is a high frequency crystal-based PLL synchronizer designed as a module level subsystem for easy incorporation into telecommunication equipment.
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SY0002B
SY0002B
889mm)
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disadvantage of numeric water level indicator
Abstract: No abstract text available
Text: Dual/Quad Input Network Clock Generator/Synchronizer AD9547 FEATURES APPLICATIONS Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Automatic/manual holdover and reference switchover
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AD9547
30-bit
64-Lead
CP-64-4)
AD9547BCPZ
AD9547BCPZ-REEL7
AD9547/PCBZ
091707-C
disadvantage of numeric water level indicator
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GR-253-CORE
Abstract: ZL30119 ZL30119GGG ZL30119GGG2 "network interface cards"
Text: ZL30119 SONET/SDH Low Jitter Line Card Synchronizer Data Sheet December 2005 A full Design Manual is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30119GGG 100 Pin CABGA Trays ZL30119GGG2 100 Pin CABGA*
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ZL30119
ZL30119GGG
ZL30119GGG2
-40oC
GR-253-CORE
ZL30119
ZL30119GGG
"network interface cards"
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F 9322
Abstract: DP8459 floppy disk magnetic read write head assembly IC 566 vco national semiconductor logic 566 vco kpc 817 DP8459TP-10 DP8459V-10 DP8459V-25
Text: DP8459 All-Code Data Synchronizer General Description The DP8459 Data Synchronizer is an integrated phase locked loop circuit which has been designed for application in magnetic hard disk, flexible floppy disk, optical disk, and tape drive memory systems for data re-synchronization and
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DP8459
28-pin
ds009322
F 9322
floppy disk magnetic read write head assembly
IC 566 vco
national semiconductor logic
566 vco
kpc 817
DP8459TP-10
DP8459V-10
DP8459V-25
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ADT2T-1T-1P
Abstract: AD9739 AD9739BBCZ docsis 9508g ADCLK914 593 ph 9425 ADT2T INTEL Core i7 860 AVDD33
Text: 14-Bit, 2500 MSPS, RF Digital-to-Analog Converter AD9739 FUNCTIONAL BLOCK DIAGRAM RESET SYNC_IN_P SYNC_IN_N DB0[13:0]P DB0[13:0]N DB1[13:0]P DB1[13:0]N LVDS DRIVER CLOCK DISTRIBUTION SYNCHRONIZER DCI_P DCI_N LVDS DRIVER SYNC_OUT_P SYNC_OUT_N LVDS RECEIVER
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14-Bit,
AD9739
10-BIT
160-Ball
BC-160-1
ADT2T-1T-1P
AD9739
AD9739BBCZ
docsis
9508g
ADCLK914
593 ph 9425
ADT2T
INTEL Core i7 860
AVDD33
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FEC 0642 RoHS
Abstract: AD9584 lfcsp_VQ package 0E-18 06d6 06AC
Text: Quad/Octal Input Network Clock Generator/Synchronizer AD9548 FEATURES APPLICATIONS Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Auto/manual holdover and reference switchover
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AD9548
30-bit
30-bLead
CP-88-2)
AD9548BCPZ
AD9548BCPZ-REEL7
AD9548/PCBZ
88-Lead
CP-88-2
FEC 0642 RoHS
AD9584
lfcsp_VQ package
0E-18
06d6
06AC
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