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    SY100S838ZCTR Search Results

    SY100S838ZCTR Datasheets (2)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    SY100S838ZCTR Micrel Semiconductor (Divide 1, Divide 2/3) OR (Divide 2, Divide 4/6) CLOCK GENERATION CHIP Original PDF
    SY100S838ZC-TR Microchip Technology Integrated Circuits (ICs) - Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers - IC CLOCK GEN 3.3V/5V 20-SOIC Original PDF

    SY100S838ZCTR Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    113006

    Abstract: SY100S838ZC SY100S838 SY100S838L SY100S838LZC SY100S838LZCTR SY100S838ZCTR SY100S838ZI SY100S838LZGTR
    Text: ÷1, ÷2/3 OR (÷2, ÷4/6) CLOCK GENERATION CHIP Micrel, Inc. Precision Edge Precision SY100S838 Edge® SY100S838L SY100S838 SY100S838L FEATURES • ■ ■ ■ ■ ■ 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable


    Original     		PDF SY100S838 SY100S838L 20-pin SY100S838/L M9999-113006 113006 SY100S838ZC SY100S838 SY100S838L SY100S838LZC SY100S838LZCTR SY100S838ZCTR SY100S838ZI SY100S838LZGTR

    SY100S838

    Abstract: SY100S838L SY100S838LZC SY100S838LZCTR SY100S838ZC SY100S838ZCTR 100S838L
    Text: SYNERGY ClockWorks SY100S838 ClockWorks™ SY100S838L ÷1, ÷2/3 OR (÷2, ÷4/6) CLOCK GENERATION CHIP SEMICONDUCTOR SYNERGY SY100S838 SY100S838L SEMICONDUCTOR FEATURES DESCRIPTION • 3.3V and 5V power supply options ■ 50ps output-to-output skew ■ Synchronous enable/disable


    Original     		PDF SY100S838 SY100S838L SY100S838ZC Z20-1 SY100S838ZCTR SY100S838LZC SY100S838 SY100S838L SY100S838LZC SY100S838LZCTR SY100S838ZC SY100S838ZCTR 100S838L

    SY100S838

    Abstract: SY100S838L SY100S838LZC SY100S838LZCTR SY100S838ZC SY100S838ZCTR
    Text: ÷1, ÷2/3 OR (÷2, ÷4/6) CLOCK GENERATION CHIP FEATURES • ■ ■ ■ ■ ■ DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are


    Original     		PDF SY100S838/L SY100S838LZI Z20-1 SY100S838LZITR SY100S838 SY100S838L Z20-1) SY100S838 SY100S838L SY100S838LZC SY100S838LZCTR SY100S838ZC SY100S838ZCTR

    SY100S838

    Abstract: SY100S838L SY100S838LZC SY100S838LZCTR SY100S838ZC SY100S838ZCTR
    Text: ClockWorks SY100S838 SY100S838L FINAL ÷1, ÷2/3 OR (÷2, ÷4/6) CLOCK GENERATION CHIP FEATURES • ■ ■ ■ ■ ■ DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are


    Original     		PDF SY100S838 SY100S838L SY100S838/L 0SY100S838LZI Z20-1 SY100S838LZITR Z20-1) SY100S838 SY100S838L SY100S838LZC SY100S838LZCTR SY100S838ZC SY100S838ZCTR

    100S838L

    Abstract: No abstract text available
    Text: V • SYNERGY 2n s o r ' : a 4 ei : ;.o c k î î e n f r a m ^ Z M c v H a w .„ if \8 S E M IC O N D U C 1O R F EA TU R E S D ES C R IPTIO N • 3.3V and 5V pow er supply options ■ 50ps output-to-output skew ■ Synchronous enable/disable ■ M aster Reset for synchronization


    OCR Scan     		PDF 75Ki2 20-pin SY100S838ZC SY100S838ZCTR SY100S838LZC SY100S838LZCTR Z20-1 Z20-1 100S838L

    Untitled

    Abstract: No abstract text available
    Text: >0 » SYNERGY -1 ,^ /3 OR (*2, *4/6) c l o c k g e n e r a tio n chip SEMICONDUCTOR • 3.3V and 5V power supply options ■ 50ps output-to-output skew ■ Synchronous enable/disable ■ Master Reset for synchronization ■ Internal 75KÌ2 input pull-down resistors


    OCR Scan     		PDF 20-pin

    Untitled

    Abstract: No abstract text available
    Text: +1, +2/3 OR (+2, * 4 /6 ) c l o c k g e n e r a t i o n c h ip SYNERG Y C'QS 0 S 8 3 8 s y io o s s 3 8 l SEMICONDUCTOR DESCRIPTION FEATURES • 3.3V and 5V power supply options ■ 50ps output-to-output skew ■ Synchronous enable/disable ■ Master Reset for synchronization


    OCR Scan     		PDF 0S838 20-pin SY100S838/L

    Untitled

    Abstract: No abstract text available
    Text: M , +2/3 OR +2, +4/6) CLO CK GENERATIO N CHIP SYNERGY S E M IC O N D U C T O R FEATURES • ■ ■ ■ ■ ■ C'°S Y^0S838 Sy 10Qs83bl S Y 100S 838L DESCRIPTION 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization


    OCR Scan     		PDF 0S838 10Qs83bl 838/L SY100S838ZC SY100S838ZCTR SY100S838LZC SY1OOS838LZCTR Z20-1

    Untitled

    Abstract: No abstract text available
    Text: >0 » SYNERGY -1, ^2/3 OR (-2, ^1/6) c l o c k g e n e r a tio n chip SEMICONDUCTOR • 3.3V and 5V power supply options ■ 50ps output-to-output skew ■ Synchronous enable/disable ■ Master Reset for synchronization ■ Internal 75KÌ2 input pull-down resistors


    OCR Scan     		PDF 20-pin