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    STRATIX V Search Results

    STRATIX V Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    LM2917MX/NOPB Texas Instruments Frequency to Voltage Converter 14-SOIC -40 to 85 Visit Texas Instruments Buy
    LM2907MX/NOPB Texas Instruments Frequency to Voltage Converter 14-SOIC -40 to 85 Visit Texas Instruments Buy
    LM2917M/NOPB Texas Instruments Frequency to Voltage Converter 14-SOIC -40 to 85 Visit Texas Instruments Buy
    LM2907M/NOPB Texas Instruments Frequency to Voltage Converter 14-SOIC -40 to 85 Visit Texas Instruments Buy
    LM2917N-8/NOPB Texas Instruments Frequency to Voltage Converter 8-PDIP -40 to 85 Visit Texas Instruments Buy

    STRATIX V Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    EP2S15

    Abstract: EP2S180 EP2S30 EP2S60 EP2S90 EPC16 EPCS16 EPCS64 pull-up resistor 10K EPCS 16 soic
    Text: 7. Configuring Stratix II & Stratix II GX Devices SII52007-4.4 Introduction Stratix II and Stratix II GX devices use SRAM cells to store configuration data. Because SRAM memory is volatile, configuration data must be downloaded to Stratix II and Stratix II GX devices each time the device


    Original     		SII52007-4 EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 EPC16 EPCS16 EPCS64 pull-up resistor 10K EPCS 16 soic PDF

    pin configuration of latch switch

    Abstract: EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 EPC16 EPCS128 EPCS16 EPCS64
    Text: 13. Configuring Stratix II & Stratix II GX Devices SII52007-4.5 Introduction Stratix II and Stratix II GX devices use SRAM cells to store configuration data. Because SRAM memory is volatile, configuration data must be downloaded to Stratix II and Stratix II GX devices each time the device


    Original     		SII52007-4 pin configuration of latch switch EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 EPC16 EPCS128 EPCS16 EPCS64 PDF

    EP2S15

    Abstract: EP2S180 EP2S30 EP2S60 EP2S90 EPC16 EPCS128 EPCS16 EPCS64
    Text: 7. Configuring Stratix II and Stratix II GX Devices SII52007-4.5 Introduction Stratix II and Stratix II GX devices use SRAM cells to store configuration data. Because SRAM memory is volatile, configuration data must be downloaded to Stratix II and Stratix II GX devices each time the device


    Original     		SII52007-4 EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 EPC16 EPCS128 EPCS16 EPCS64 PDF

    LHF16J06

    Abstract: EPC16 0x00010040
    Text: 2. Remote System Configuration with Stratix & Stratix GX Devices S52015-3.1 Introduction Altera Stratix® and Stratix GX devices are the first programmable logic devices PLDs featuring dedicated support for remote system configuration. Using remote system configuration, a Stratix or Stratix GX


    Original     		S52015-3 LHF16J06 EPC16 0x00010040 PDF

    0X001F0000

    Abstract: POF Formats Altera 0x00010040 stratus EPC16 LHF16J06
    Text: 12. Remote System Configuration with Stratix & Stratix GX Devices S52015-3.1 Introduction Altera Stratix® and Stratix GX devices are the first programmable logic devices PLDs featuring dedicated support for remote system configuration. Using remote system configuration, a Stratix or Stratix GX


    Original     		S52015-3 0X001F0000 POF Formats Altera 0x00010040 stratus EPC16 LHF16J06 PDF

    altera stratix II fpga

    Abstract: EPCS16 EPCS64 SSTL-18 18x18-Bit
    Text: White Paper Architectural Differences Between Stratix II and Stratix Devices Introduction Stratix II devices, Altera's next-generation high-density FPGAs, are based on the award-winning Stratix device architecture. Building on the innovations that made Stratix FPGAs an instant success, Stratix II devices provide new


    Original     		PDF

    EP20K200E

    Abstract: EP20K400E
    Text: 10. Transitioning APEX Designs to Stratix & Stratix GX Devices S52012-3.0 Introduction Stratix and Stratix GX devices are Altera’s next-generation, system-ona-programmable-chip SOPC solution. Stratix and Stratix GX devices simplify the block-based design methodology and bridge the gap


    Original     		S52012-3 EP20K200E EP20K400E PDF

    Untitled

    Abstract: No abstract text available
    Text: Implementing Stratix III and Stratix IV Programmable I/O Delay Settings in the Quartus II Software Application Note 474 August 2013, ver. 1.3 Introduction Altera Stratix® III and Stratix IV series devices have a very versatile I/O architecture. Included in the various features of the Stratix III I/O are


    Original     		PDF

    JESD8-15

    Abstract: HSTL standards SSTL-18 class 8 date sheet EIA standards 15-V
    Text: 10. Selectable I/O Standards in Stratix II and Stratix II GX Devices SII52004-4.6 Introduction This chapter provides guidelines for using industry I/O standards in Stratix II and Stratix II GX devices, including: • ■ ■ ■ ■ Stratix II and Stratix II GX I/O


    Original     		SII52004-4 JESD8-15 HSTL standards SSTL-18 class 8 date sheet EIA standards 15-V PDF

    HSTL standards

    Abstract: DDR2 sstl_18 class I 15-V SSTL-18
    Text: 4. Selectable I/O Standards in Stratix II & Stratix II GX Devices SII52004-4.5 Introduction This chapter provides guidelines for using industry I/O standards in Stratix II and Stratix II GX devices, including: • ■ ■ ■ ■ Stratix II & Stratix II GX I/O


    Original     		SII52004-4 HSTL standards DDR2 sstl_18 class I 15-V SSTL-18 PDF

    HSTL standards

    Abstract: class sstl SSTL-18 EIA standards 15-V SSTL18 JESD89A DDR2 sstl_18 class I
    Text: 4. Selectable I/O Standards in Stratix II and Stratix II GX Devices SII52004-4.6 Introduction This chapter provides guidelines for using industry I/O standards in Stratix II and Stratix II GX devices, including: • ■ ■ ■ ■ Stratix II and Stratix II GX I/O


    Original     		SII52004-4 HSTL standards class sstl SSTL-18 EIA standards 15-V SSTL18 JESD89A DDR2 sstl_18 class I PDF

    EP1S60

    Abstract: No abstract text available
    Text: Using TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices November 2002, ver. 2.0 Application Note 203 Introduction Stratix and Stratix GX devices feature the TriMatrix™ memory structure, composed of three sizes of embedded RAM blocks. TriMatrix


    Original     		512-bit 512-Kbit EP1S60 PDF

    BT 1610

    Abstract: 672-FBGA FBGA 12x12 heat sink FBGA-484 datasheet JEDEC FBGA EP2S15 EP2S180 EP2S30 EP2S60 EP2S90
    Text: 16. Package Information for Stratix II & Stratix II GX Devices SII52010-4.3 Introduction This chapter provides package information for Altera Stratix® II and Stratix II GX devices, including: • ■ ■ Device and package cross reference Thermal resistance values


    Original     		SII52010-4 EP2S15 EP2S30 EP2S60 BT 1610 672-FBGA FBGA 12x12 heat sink FBGA-484 datasheet JEDEC FBGA EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 PDF

    FBGA 152

    Abstract: 68 ball fbga thermal resistance FBGA1020 78 ball fbga thermal resistance EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 FBGA-484
    Text: 10. Package Information for Stratix II & Stratix II GX Devices SII52010-4.3 Introduction This chapter provides package information for Altera Stratix® II and Stratix II GX devices, including: • ■ ■ Device and package cross reference Thermal resistance values


    Original     		SII52010-4 EP2S15 EP2S30 EP2S60 FBGA 152 68 ball fbga thermal resistance FBGA1020 78 ball fbga thermal resistance EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 FBGA-484 PDF

    HC1S30F780

    Abstract: EP1S30F780C6 M-512
    Text: 14. Design Guidelines for HardCopy Stratix Performance Improvement H51027-1.3 Introduction Advanced design techniques using Altera HardCopy® Stratix® devices can yield tremendous performance improvements over the design implemented in a Stratix FPGA device. After you verify your Stratix


    Original     		H51027-1 HC1S30F780 EP1S30F780C6 M-512 PDF

    HC1S30F780

    Abstract: EP1S30F780C6
    Text: 6. Design Guidelines for HardCopy Stratix Performance Improvement H51027-1.4 Introduction Advanced design techniques using Altera HardCopy ® Stratix® devices can yield tremendous performance improvements over the design implemented in a Stratix FPGA device. After you verify your Stratix


    Original     		H51027-1 HC1S30F780 EP1S30F780C6 PDF

    2f 1001

    Abstract: 1100 11010 FD-111 transistor D313 equivalent
    Text: 6. Specifications & Additional Information SIIGX52004-3.1 Transceiver Blocks Table 6–1 shows the transceiver blocks for Stratix II GX and Stratix GX devices and compares their features. Table 6–1. Stratix II GX Features Versus Stratix GX Features Part 1 of 2


    Original     		SIIGX52004-3 OC-12, OC-48, OC-96) 2f 1001 1100 11010 FD-111 transistor D313 equivalent PDF

    S5200-1

    Abstract: EP1S60 S52001-3
    Text: 1. General-Purpose PLLs in Stratix & Stratix GX Devices S52001-3.2 Introduction Stratix and Stratix GX devices have highly versatile phase-locked loops PLLs that provide robust clock management and synthesis for on-chip clock management, external system clock management, and high-speed


    Original     		S52001-3 S5200-1 EP1S60 PDF

    DESIGN AND IMPLEMENTATION 16-BIT BARREL SHIFTER

    Abstract: Virtex-4 barrel shifter barrel shifter with flip flop 16-bit adder code using xilinx code
    Text: White Paper Stratix II vs. Virtex-4 Performance Comparison Altera Stratix® II devices use a new and innovative logic structure called the adaptive logic module ALM to make Stratix II devices the industry’s biggest and fastest FPGAs. With the Stratix II ALM


    Original     		90-nm DESIGN AND IMPLEMENTATION 16-BIT BARREL SHIFTER Virtex-4 barrel shifter barrel shifter with flip flop 16-bit adder code using xilinx code PDF

    Untitled

    Abstract: No abstract text available
    Text: Errata Sheet for Stratix V Devices ES-01034-1.6 Errata Sheet This errata sheet provides information about known device issues affecting Stratix V production devices. Production Device Issues for Stratix V Devices Table 1 lists the issues and the affected Stratix V production devices.


    Original     		ES-01034-1 PDF

    Untitled

    Abstract: No abstract text available
    Text: JTAG Boundary-Scan Testing in Stratix V Devices 10 2013.05.06 SV51012 Subscribe Feedback This chapter describes the boundary-scan test BST features in Stratix V devices. Related Information Stratix V Device Handbook: Known Issues Lists the planned updates to the Stratix V Device Handbook chapters.


    Original     		SV51012 PDF

    UniPHY

    Abstract: 1932-pin SV1008-1
    Text: 7. External Memory Interfaces in Stratix V Devices SV1008-1.0 This chapter describes external memory interfaces available with Stratix V devices, as well as the silicon capabilities of Stratix V devices to support external memory interfaces. Stratix V devices provide an efficient architecture to quickly and easily fit


    Original     		SV1008-1 UniPHY 1932-pin PDF

    video transmiter

    Abstract: hd sdi receiver DDR333 EPC16 MK2069 27mhz transmitter and receiver hd receiver 27mhz transmitter 27mhz receiver 20 pin header connector
    Text: Stratix GX Video Demonstration Board Data Sheet May 2004, version 1.0 Introduction f The Altera Stratix® GX Video Demonstration Board is an evaluation platform that demonstrates the superior video performance and key features of Altera’s Stratix GX devices. The Stratix GX board and Altera’s


    Original     		SMPTE-292M SMPTE-259M video transmiter hd sdi receiver DDR333 EPC16 MK2069 27mhz transmitter and receiver hd receiver 27mhz transmitter 27mhz receiver 20 pin header connector PDF

    pin configuration 1K variable resistor

    Abstract: TMs 1122 pin configuration 20K variable resistor EP1S60 EPC16
    Text: 11. Configuring Stratix & Stratix GX Devices S52013-3.2 Introduction You can configure Stratix and Stratix GX devices using one of several configuration schemes. All configuration schemes use either a microprocessor, configuration device, or a download cable. See


    Original     		S52013-3 pin configuration 1K variable resistor TMs 1122 pin configuration 20K variable resistor EP1S60 EPC16 PDF