ST10

Abstract: ST10R165 ST10R165BQ1 st10 Bootstrap ST10 FAMILY PROGRAMMING MANUAL
Contextual Info: ST10R165BQ1 16-BIT ROMLESS MICROCONTROLLER DATASHEET • ■ ■ ■ ■ ■ October 1997 The information in this datasheet is subject to change OSC CPU-Core Internal Ram 16 16 16 Watchdog PEC Interrupt C ontroller Port 6 ■ ■ ■ ■ 6 SSC GPT2 Port 5

Contextual Info: SGS-THOMSON ST10R 165 iM ig ia o iiU K g T r M n 16-BIT ROMLESS MICROCONTROLLER PRELIMINARY DATA High performance 16-bit CPU with 4-stage pipeline 100 nsinstruction cycle timeat20-MHz CPU clock 500 ns multiplication 16 x 16 bits , 1 jos division (32/16 bit)

Contextual Info: n = T S G S -IH O M S O N *7 M , [MiMi[Liginia R!ine§ s n om 65BQ1 16-BIT ROMLESS MICROCONTROLLER DATASHEET High performance CPU • 16-bit CPU with 4-stage pipeline ■ 80ns instruction cycle time at 25MHz CPU clock ■ 400ns 16x16 bit multiplication CPU-Core

SERVICE MANUAL tv TCL

Abstract: 21A18 ST10R165BQ1 PQFP100 ST10 ST10R165 NE 555 SGS tcl tv system ic st10 Bootstrap T41R
Contextual Info: « S G S -T H O M S O N k7 Ä M1H(B[SI@H IU g ( g i r » [ C T n ( g g S T 1 0 R 1 6 5 16-BIT ROMLESS MICROCONTROLLER PRELIMINARY DATA • High performance 16-bit CPU with 4-stage pipeline ■ 100nsinstructioncycletimeat20-MHzCPUclock ■ 500 ns multiplication (16 x 16 bits , 1 |xs division

st10 Bootstrap

Abstract: 110H-114H
Contextual Info: ST10R165 16-BIT ROMLESS MICROCONTROLLER ADVANCE DATA • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High performance 16-bit CPU with 4-stage pipeline 100 nsinstructioncycle timeat20-MHzCPUclock 500 ns multiplication 16 x 16 bits , 1 µs division