LV125A
Abstract: 74lv125a A115-A C101 SN54LV125A SN74LV125A
Text: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES124F – DECEMBER 1997 – REVISED JANUARY 2001 D D D D SN54LV125A . . . J OR W PACKAGE SN74LV125A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce
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SN54LV125A,
SN74LV125A
SCES124F
SN54LV125A
000-V
A114-A)
A115-A)
SSYZ010L
LV125A
74lv125a
A115-A
C101
SN54LV125A
SN74LV125A
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HC574
Abstract: SN54HC574 SN74HC574 SN74HC574DBR SN74HC574DW SN74HC574DWR SN74HC574N SN74HC574PWR SNJ54HC574J SNJ54HC574W
Text: SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS148D – DECEMBER 1982 – REVISED JANUARY 2001 D SN54HC574 . . . J OR W PACKAGE SN74HC574 . . . DB, DW, N, OR PW PACKAGE TOP VIEW High-Current 3-State Noninverting Outputs
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SN54HC574,
SN74HC574
SCLS148D
SN54HC574
SSYZ010L
HC574
SN54HC574
SN74HC574
SN74HC574DBR
SN74HC574DW
SN74HC574DWR
SN74HC574N
SN74HC574PWR
SNJ54HC574J
SNJ54HC574W
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MAX734
Abstract: TPS2211 TPS2212 TPS2212IDB TPS2212IDBR TPS6734
Text: TPS2212 SINGLE-SLOT, PARALLEL INTERFACE POWER SWITCH FOR LOW POWER PC CARD SLOTS SLVS193A – APRIL 1999 – REVISED JANUARY 2001 D D D D D D D D D D Fully Integrated VCC and Vpp Switching for Low Power Single-Slot PC Card Interface DB PACKAGE TOP VIEW
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TPS2212
SLVS193A
160-m
16-Pin
SSYZ010L
MAX734
TPS2211
TPS2212
TPS2212IDB
TPS2212IDBR
TPS6734
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SN75185
Abstract: SN75C185 SN75LP196 SN75LPE185 SN75LPE185DBR
Text: SN75LPE185 LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS WITH ENABLE SLLS256E – DECEMBER 1996 – REVISED JANUARY 2001 D D D D D D D D D D D D Single-Chip RS-232 Interface for IBM PC Compatible Serial Port Designed to Transmit and Receive 4-µs Pulses
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SN75LPE185
RS-232
SLLS256E
TIA/EIA-232-F
SN75LP196
SSYZ010L
SN75185
SN75C185
SN75LP196
SN75LPE185
SN75LPE185DBR
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SLVA079
Abstract: No abstract text available
Text: ą UC285Ć1, UC285Ć2, UC285Ć3, UC285ĆADJ, UC385Ć1, UC385Ć2, UC385Ć3, UC385ĆADJ FAST TRANSIENT RESPONSE 5ĆA LOWĆDROPOUT REGULATOR SLUS212D – NOVEMBER 1999 – REVISED JANUARY 2001 D D D D D D D D Fast Transient Response 10-mA to 5-A Load Current
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UC2851,
UC2852,
UC2853,
UC285ADJ,
UC3851,
UC3852,
UC3853,
UC385ADJ
SLUS212D
10-mA
SLVA079
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voltage regulator 3 pin 5A
Abstract: UCCx81-ADJ
Text: ą UC285Ć1, UC285Ć2, UC285Ć3, UC285ĆADJ, UC385Ć1, UC385Ć2, UC385Ć3, UC385ĆADJ FAST TRANSIENT RESPONSE 5ĆA LOWĆDROPOUT REGULATOR SLUS212D – NOVEMBER 1999 – REVISED JANUARY 2001 D D D D D D D D Fast Transient Response 10-mA to 5-A Load Current
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UC2851,
UC2852,
UC2853,
UC285ADJ,
UC3851,
UC3852,
UC3853,
UC385ADJ
SLUS212D
10-mA
voltage regulator 3 pin 5A
UCCx81-ADJ
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A115-A
Abstract: C101 SN54LV175A SN74LV175A 74LV175A
Text: SN54LV175A, SN74LV175A QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR SCLS400D – APRIL 1998 – REVISED JANUARY 2001 D D D D D description The ’LV175A devices are quadruple D-type flip-flops designed for 2-V to 5.5-V VCC operation. These devices have a direct clear CLR input and
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SN54LV175A,
SN74LV175A
SCLS400D
LV175A
SN54LV175A
SSYZ010L
A115-A
C101
SN54LV175A
SN74LV175A
74LV175A
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UC285
Abstract: UC382 UC385 UC2853 UC3852
Text: ą UC285Ć1, UC285Ć2, UC285Ć3, UC285ĆADJ, UC385Ć1, UC385Ć2, UC385Ć3, UC385ĆADJ FAST TRANSIENT RESPONSE 5ĆA LOWĆDROPOUT REGULATOR SLUS212D – NOVEMBER 1999 – REVISED JANUARY 2001 D D D D D D D D Fast Transient Response 10-mA to 5-A Load Current
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UC2851,
UC2852,
UC2853,
UC285ADJ,
UC3851,
UC3852,
UC3853,
UC385ADJ
SLUS212D
10-mA
UC285
UC382
UC385
UC2853
UC3852
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TMS320C5402
Abstract: tms320vC5402 starter kit board diagram TMS320C5402 instruction mcbsp1 tms320vC5402 starter kit ADS8320 TMS320VC5402 ADS8321 C5402 sbas108
Text: Application Report SLAA118 – January 2001 Interfacing the ADS8320 to the TMS320C5402 DSP Lijoy Philipose Data Acquisition Applications ABSTRACT This report presents a method for interfacing the ADS8320 16-bit SAR analog-to-digital converter to the TMS320C5402 DSP. In an effort to reduce development time, the source
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SLAA118
ADS8320
TMS320C5402
16-bit
SSYZ010L
tms320vC5402 starter kit board diagram
TMS320C5402 instruction
mcbsp1
tms320vC5402 starter kit
TMS320VC5402
ADS8321
C5402
sbas108
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EPF20K
Abstract: EPF10KE 476 20k cap EP10K APEX LINE AMP 484-BGA ep20k200 pin out ep20k apex board PT650x
Text: Application Report SLVA087 – January 2001 Power-Supply Solutions for Multivolt Altera FLEX 10KE and APEX 20K/KE FPGAs Bill Milus AAP Power Management ABSTRACT This report is a reference for design engineers inexperienced with multivoltage devices but who are using Altera 2.5-V and 1.8-V multivoltage APEX 20K/20KE and FLEX 10KE
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SLVA087
20K/KE
20K/20KE
SSYZ010L
EPF20K
EPF10KE
476 20k cap
EP10K
APEX LINE AMP
484-BGA
ep20k200 pin out
ep20k apex board
PT650x
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LV240A
Abstract: A115-A C101 SN54LV240A SN74LV240A
Text: SN54LV240A, SN74LV240A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS384E – SEPTEMBER 1997 – REVISED JANUARY 2001 D D D D SN54LV240A . . . J OR W PACKAGE SN74LV240A . . . DB, DGV, DW, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)
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SN54LV240A,
SN74LV240A
SCLS384E
SN54LV240A
000-V
A114-A)
A115-A)
SSYZ010L
LV240A
A115-A
C101
SN54LV240A
SN74LV240A
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MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER
Abstract: A115-A C101 SN54LV221A SN74LV221A
Text: SN54LV221A, SN74LV221A DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS SCLS450C – DECEMBER 1999 – REVISED JANUARY 2001 D D D D D 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Schmitt-Trigger Circuitry on A, B, and CLR
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SN54LV221A,
SN74LV221A
SCLS450C
000-V
A114-A)
A115-A)
SN54LV221A
SSYZ010L
MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER
A115-A
C101
SN54LV221A
SN74LV221A
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A115-A
Abstract: C101 SN54LV139A SN74LV139A 74LV139A
Text: SN54LV139A, SN74LV139A DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCLS396C – APRIL 1998 – REVISED JANUARY 2001 D D D D 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Designed Specifically for High-Speed Memory Decoders and Data-Transmission
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SN54LV139A,
SN74LV139A
SCLS396C
000-V
A114-A)
A115-A)
SN54LV139A
SSYZ010L
A115-A
C101
SN54LV139A
SN74LV139A
74LV139A
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MO-150
Abstract: TPS2202AI TPS2202AIDBR TPS2202AIDFR
Text: TPS2202AI DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER SLVS123B – SEPTEMBER 1995 – REVISED JANUARY 2001 D D D D D D D D D D D Fully Integrated VCC and Vpp Switching for Dual-Slot PC Card Interface P2C 3-Lead Serial Interface Compatible
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TPS2202AI
SLVS123B
30-Pin
160-m
SSYZ010L
MO-150
TPS2202AI
TPS2202AIDBR
TPS2202AIDFR
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SN75185
Abstract: SN75C185 SN75LP1185 SN75LP1185DBR SN75LP1185DW SN75LP1185N SN75LP196
Text: SN75LP1185 LOW-POWER MULTIPLE RS-232 DRIVERS AND RECEIVERS SLLS335A – JANUARY 1999 – REVISED JANUARY 2001 D D D D D D D D D D D DB, DW, OR N PACKAGE TOP VIEW Single-Chip TIA/EIA-232-F Interface for IBM PC/AT Serial Port Designed to Transmit and Receive 4-µs
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SN75LP1185
RS-232
SLLS335A
TIA/EIA-232-F
21-mW
15-kV,
TIA/EIA-232-F
SN75LP196
SSYZ010L
SN75185
SN75C185
SN75LP1185
SN75LP1185DBR
SN75LP1185DW
SN75LP1185N
SN75LP196
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LV123A
Abstract: A115-A C101 SN54LV123A SN74LV123A
Text: SN54LV123A, SN74LV123A DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS SCLS393D – APRIL 1998 – REVISED JANUARY 2001 D D D D D D D D D 2-V to 5.5-V VCC Operation Typical VOLP Output Ground Bounce <0.8 V at VCC = 3.3 V, TA = 25°C
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SN54LV123A,
SN74LV123A
SCLS393D
SSYZ010L
LV123A
A115-A
C101
SN54LV123A
SN74LV123A
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LINEAR MARKING
Abstract: AB245 ti marking military part identification marking TI BINARY DATE CODE SN74ABT245DW AB245A TI date code TI Actual Topside Mark SN7400N
Text: Application Report SZZA020B - January 2001 Standard Linear & Logic Semiconductor Marking Guidelines James Huckabee and Cles Troxtell Standard Linear & Logic ABSTRACT The Texas Instruments TI Standard Linear & Logic (SLL) business group uses complex methods to assign device topside marking. These methods ensure that correct component
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SZZA020B
SSYZ010L
LINEAR MARKING
AB245
ti marking
military part identification marking
TI BINARY DATE CODE
SN74ABT245DW
AB245A
TI date code
TI Actual Topside Mark
SN7400N
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LV08A
Abstract: 74LV08A A115-A C101 SN54LV08A SN74LV08A
Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387E – SEPTEMBER 1997 – REVISED JANUARY 2001 D D D D SN54LV08A . . . J OR W PACKAGE SN74LV08A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)
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SN54LV08A,
SN74LV08A
SCLS387E
SN54LV08A
000-V
A114-A)
A115-A)
SSYZ010L
LV08A
74LV08A
A115-A
C101
SN54LV08A
SN74LV08A
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74LV138A
Abstract: A115-A C101 LV138A SN54LV138A SN74LV138A
Text: SN54LV138A, SN74LV138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS395D – APRIL 1998 – REVISED JANUARY 2001 D D D D D D 2-V to 5.5-V VCC Operation Typical VOLP Output Ground Bounce <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)
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SN54LV138A,
SN74LV138A
SCLS395D
000-V
A114-A)
A115-A)
SN54LV138A
SSYZ010L
74LV138A
A115-A
C101
LV138A
SN54LV138A
SN74LV138A
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LW040A
Abstract: 74LV4040A RCTR12 A115-A C101 SN54LV4040A SN74LV4040A
Text: SN54LV4040A, SN74LV4040A 12-BIT ASYNCHRONOUS BINARY COUNTERS SCES226C – APRIL 1999 – REVISED JANUARY 2001 D D D D D D D QL QF QE QG QD QC QB GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QK QJ QH QI CLR CLK QA SN54LV4040A . . . FK PACKAGE TOP VIEW QE
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SN54LV4040A,
SN74LV4040A
12-BIT
SCES226C
SN54LV4040A
LV4040A
SSYZ010L
LW040A
74LV4040A
RCTR12
A115-A
C101
SN54LV4040A
SN74LV4040A
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