SSTL_3, 3.3 V Search Results

SSTL_3, 3.3 V Result Highlights (3)

Part	Manufacturer	Description
CDCV857ADGGR	Texas Instruments	2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85
CDCV857ADGGG4	Texas Instruments	2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85
CDCV857ADGG	Texas Instruments	2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85

SSTL_3, 3.3 V Price and Stock

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Bourns Inc 2124-V-RC Inductor High Current Toroid 1000uH/559.2uH 15% 1KHz 1.3A 400mOhm DCR RDL
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Onlinecomponents.com	2124-V-RC		1,666			1 - 10 - 100 - 1000 $1.21 10000 $1.169	Buy Now
Eaton Bussmann S506-V-400-R S506 400MA -v Buss Td Bk 100 Box -r
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Onlinecomponents.com	S506-V-400-R		1,000			1 - 10 $4.97 100 $4.49 1000 $1.06 10000 $1.06	Buy Now
Neutrik USA Inc NLJ2MD-V speakON Combo - 2 pole combination of speakON socket and 1/4" jack receptacle - vertical pcb mount - same pcb footprint and panel cut out as NL4MD-V First speakON / jack hybrid panel mount connector combining the speakON chassis connector with a 1/4" 2
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Onlinecomponents.com	NLJ2MD-V		838			1 - 10 $3.56 100 $3.08 1000 $2.51 10000 $2.35	Buy Now
Neutrik USA Inc NL4MDXX-V Loudspeaker Connectors Receptacle - 4 Pole - PCBV - Countersunk Thru Holes For Countersunk Machine Screws (e.g.: M3 - 4-40).
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Onlinecomponents.com	NL4MDXX-V		500			1 - 10 $4.28 100 $3.47 1000 $3.07 10000 $2.92	Buy Now
Bourns Inc 2119-V-RC Inductor High Current Toroid 390uH/250.1uH 15% 1KHz 1.7A 250mOhm DCR RDL
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Onlinecomponents.com	2119-V-RC		272			1 - 10 - 100 $1.655 1000 $1.343 10000 $1.169	Buy Now

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SSTL_3, 3.3 V Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: SN74SSTL16837A 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS675G – SEPTEMBER 1996 – REVISED SEPTEMBER 1998 D D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Supports SSTL_3 Signal Inputs and Outputs	Original	SN74SSTL16837A 20-BIT SCBS675G	PDF
1523m Abstract: MAN09 ICS1523 1523MLFT Text: ICS1523 Video Clock Synthesizer with I2C Programmable Delay General Description Features The ICS1523 is a low-cost, high-performance frequency generator. It is well suited to general purpose phase controlled clock synthesis as well as line-locked and genlocked high-resolution video	Original	ICS1523 ICS1523 1523m MAN09 1523MLFT	PDF
Untitled Abstract: No abstract text available Text: SN74SSTL16847 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A – OCTOBER 1997 – REVISED MAY 1998 D D D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB	Original	SN74SSTL16847 20-BIT SCBS709A MIL-STD-883,	PDF
SN74SSTL16837A Abstract: No abstract text available Text: SN74SSTL16837A 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS675G – SEPTEMBER 1996 – REVISED SEPTEMBER 1998 D D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Supports SSTL_3 Signal Inputs and Outputs	Original	SN74SSTL16837A 20-BIT SCBS675G SN74SSTL16837A	PDF
SN74SSTL16847 Abstract: No abstract text available Text: SN74SSTL16847 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A – OCTOBER 1997 – REVISED MAY 1998 D D D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB	Original	SN74SSTL16847 20-BIT SCBS709A MIL-STD-883, SN74SSTL16847	PDF
ICS1523MLF Abstract: ICS1523 ICS1523M ICS1523MLFT ICS1523MT 132 kv gis Text: ICS1523 Video Clock Synthesizer with I2C Programmable Delay General Description Features The ICS1523 is a low-cost, high-performance frequency generator. It is well suited to general purpose phase controlled clock synthesis as well as line-locked and genlocked high-resolution video	Original	ICS1523 ICS1523 ICS1523MLF ICS1523M ICS1523MLFT ICS1523MT 132 kv gis	PDF
Untitled Abstract: No abstract text available Text: SN74SSTL16837 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS675F – SEPTEMBER 1996 – REVISED MAY 1998 D D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Supports SSTL_3 Signal Inputs and Outputs	Original	SN74SSTL16837 20-BIT SCBS675F	PDF
Untitled Abstract: No abstract text available Text: SN74SSTL16837A 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS675G – SEPTEMBER 1996 – REVISED SEPTEMBER 1998 D D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Supports SSTL_3 Signal Inputs and Outputs	Original	SN74SSTL16837A 20-BIT SCBS675G sced006b sdyu001x scyb017a	PDF
Untitled Abstract: No abstract text available Text: SN74SSTL16847 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A - OCTOBER 1997 - REVISED MAY 1998 * Member of the Texas Instruments Widebus Family • Supports SSTL_3 Signal Inputs and Outputs DGG PACKAGE TOP VIEW I • • • • • [ 1	OCR Scan	SN74SSTL16847 20-BIT SCBS709A MIL-STD-883,	PDF
SN74SSTL16837 Abstract: No abstract text available Text: SN74SSTL16837 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS675- SEPTEMBER 1996 Member of the Texas Instruments Widebus Family DGG PACKAGE TOP VIEW Y1 [ 63 A2 GND [ 3 62 GND Y3[ 4 Y4 I 5 61 A3 60 A4 6 V DDQ Y5[ 7 Y6[ 8 59 58 V CC	OCR Scan	SN74SSTL16837 20-BIT SCBS675- SN74SSTL16837	PDF
Untitled Abstract: No abstract text available Text: HD74SSTL16837 20-bit SSTL_3 Interface Universal Bus Driver with 3-state Outputs HITACHI ADE-205-191 Z Preliminary 1st. Edition July 1, 1997 Description The HD74SSTL16837 is a 20-bit universal bus driver designed for 3.0 V to 3.6 V Vcc operation and SSTL_3 or LVTTL I/O levels.	OCR Scan	HD74SSTL16837 20-bit ADE-205-191 HD74SSTL16837 pow1835	PDF
ICS1524AM Abstract: ICS1523 ICS1524 Text: Integrated Circuit Systems, Inc. ICS1524A Dual Output Phase Controlled SSTL_3/PECL Clock Generator General Description Features The ICS1524A is a low-cost, very high-performance • frequency generator and phase controlled clock synthesizer. It is perfectly suited to phase controlled clock	Original	ICS1524A ICS1524A ICS1524AM ICS1523 ICS1524	PDF
ICS1524 Abstract: ICS1523 metal detector diagram PI Text: Integrated Circuit Systems, Inc. ICS1524 Dual Output Phase Controlled SSTL_3/PECL Clock Generator General Description Features The ICS1524 is a low-cost, very high-performance frequency generator and phase controlled clock synthesizer. It is perfectly suited to phase controlled clock	Original	ICS1524 ICS1524 ICS1523 metal detector diagram PI	PDF
Untitled Abstract: No abstract text available Text: SN74SSTL16833* 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVE WITH 3-STATE OUTPUTS SCBS675E - SEPTEMBER 1996 - REVISED DECEMBER 199 Member of the Texas Instruments Widebug* Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB	OCR Scan	SN74SSTL16833 20-BIT SCBS675E JESD17	PDF

HDMP-2630B Abstract: HDMP-2631B Text: Agilent HDMP-2630B/2631B 2.125/1.0625 GBd Serdes Circuits Data Sheet Description This data sheet describes the HDMP-2630B/2631B serdes devices for 2.125 GBd serial data rates. References to SSTL_2 in the text will also apply to SSTL_3; however, there are separate tables and figures	Original	HDMP-2630B/2631B HDMP-2630B/2631B serial13 5988-4935EN HDMP-2630B HDMP-2631B	PDF
hp 2631 Abstract: HP 2630 A 2631 hp 2630 datasheet C0603X7R160-104KNE HDMP-2630 A 2631 line receiver HDMP-2631 A 2630 RX-2 -G s Text: Agilent HDMP-2630/2631 2.125/1.0625 GBd Serdes Circuits Data Sheet Description This data sheet describes the HDMP-2630/2631 serdes devices for 2.125 GBd serial data rates. References to SSTL_2 in the text will also apply to SSTL_3; however, there are separate tables and figures	Original	HDMP-2630/2631 HDMP-2630/2631 links30/2631 5980-2110E hp 2631 HP 2630 A 2631 hp 2630 datasheet C0603X7R160-104KNE HDMP-2630 A 2631 line receiver HDMP-2631 A 2630 RX-2 -G s	PDF
Hitachi DSA00101 Abstract: HD74CDC587 Text: HD74CDC587 3.3-V Phase-lock Loop Clock Driver with 3-state Outputs Preliminary 1st. Edition September 1997 Description The HD74CDC587 is a high-performance, low-skew, low-jitter, phase-locked loop PLL clock driver. It uses a PLL to precisely align, in both frequency and phase, the clock output signals to the clock input	Original	HD74CDC587 HD74CDC587 D-85622 Hitachi DSA00101	PDF
Untitled Abstract: No abstract text available Text: SN74SSTL16837A 20-BIT SSTL 3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS S C BS 675G - S E P TE M B E R 1996 - R EVISED S E P TE M B E R 1998 Member of the Texas Instruments Widebus Family DGG PACKAGE TOP VIEW Supports SSTL 3 Signal Inputs and	OCR Scan	SN74SSTL16837A 20-BIT	PDF
Untitled Abstract: No abstract text available Text: HD74CDC587 3.3-V Phase-lock Loop Clock Driver with 3-state Outputs HITACHI Preliminary 1st. Edition September 1997 Description The HD74CDC587 is a high-performance, low-skew, low-jitter, phase-locked loop PLL clock driver. It uses a PLL to precisely align, in both frequency and phase, the clock output signals to the clock input	OCR Scan	HD74CDC587 HD74CDC587	PDF
Untitled Abstract: No abstract text available Text: 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR DESCRIPTION FEATURES • Input accepts virtually all logic standards • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature: • fMAX > 2.5Gbps 2.5GHz toggle	Original	200ps 400ps 46mW/channel 10-pin SY55857L SY55857L SY55857 K10-1)	PDF
SY55857L Abstract: SY55857UKI SY55857UKITR Text: 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR DESCRIPTION FEATURES • Input accepts virtually all logic standards • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature: • fMAX > 2.5Gbps 2.5GHz toggle	Original	200ps 400ps 46mW/channel 10-pin SY55857L Translation00 SY55857 SY55857L K10-1) SY55857UKI SY55857UKITR	PDF
Untitled Abstract: No abstract text available Text: CDC587 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _ SCAS562B- DECEMBER 1996 - REVISED JULY 1998 DQG PACKAGE TOP VIEW • Operates at 3.3-V Vqc • Distributes One Clock Input to 16 Outputs • Four Select Inputs Configure Output	OCR Scan	CDC587 SCAS562B-	PDF
Untitled Abstract: No abstract text available Text: CDC2587 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _ SCAS560B - DECEMBER 1996 - REVISED JULY 1996 • • • • • • • DQQ PACKAGE TOP VIEW CLKIN VREF FBIN Vcc FBOUT GND Vcc 1Y0 1Y1 GND VCC 1Y2 1Y3 GND V cc 2Y0 2Y1 GND V cc	OCR Scan	CDC2587 SCAS560B 25-C1 7526S	PDF
CC33G Abstract: No abstract text available Text: CDC587 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _ SCASS62B - DECEMBER 1996 - REVISED JULY 1996 Low-Output Skew and Jitter for Clock Distribution and Synchronization DOG PACKAGE TOP VIEW CLKIN [ 1 u v refÌ 2 FBIN [ 3 Veci 4 FBOUT [ 5	OCR Scan	CDC587 SCASS62B CC33G	PDF

SSTL_3, 3.3 V Search Results

SSTL_3, 3.3 V Result Highlights (3)

SSTL_3, 3.3 V Price and Stock

Bourns Inc 2124-V-RC

Eaton Bussmann S506-V-400-R

Neutrik USA Inc NLJ2MD-V

Neutrik USA Inc NL4MDXX-V

Bourns Inc 2119-V-RC

SSTL_3, 3.3 V Datasheets Context Search

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1523m

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SN74SSTL16837A

SN74SSTL16847

ICS1523MLF

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SN74SSTL16837

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ICS1524AM

ICS1524

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HDMP-2630B

hp 2631

Hitachi DSA00101

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SY55857L

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CC33G