G2992F1U
Abstract: circuit diagram of ddr ram G2992 2N7002 SSTL-18 v5856 jedec MS-012-AA
Text: G2992 Global Mixed-mode Technology Inc. 3A DDR Bus Termination Regulator Features General Description The G2992 is a linear regulator designed to meet the JEDEC SSTL-18, SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of
|
Original
|
PDF
|
G2992
G2992
SSTL-18,
41TYP
016TYP
27TYP
05TYP
G2992F1U
circuit diagram of ddr ram
2N7002
SSTL-18
v5856
jedec MS-012-AA
|
Untitled
Abstract: No abstract text available
Text: G2996 Global Mixed-mode Technology Inc. DDR I/II Termination Regulator Features General Description The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR-SDRAM. It contains a high-speed operational
|
Original
|
PDF
|
G2996
G2996
SSTL-18
|
power filter 25v
Abstract: G2996 G2996F1UF G2996F1U G2996P1U SSTL-18
Text: G2996 Global Mixed-mode Technology Inc. DDR I/II Termination Regulator Features General Description The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR-SDRAM. It contains a high-speed operational
|
Original
|
PDF
|
G2996
G2996
SSTL-18
power filter 25v
G2996F1UF
G2996F1U
G2996P1U
SSTL-18
|
Untitled
Abstract: No abstract text available
Text: G2996 Global Mixed-mode Technology Inc. DDR I/II Termination Regulator Features General Description The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR-SDRAM. It contains a high-speed operational
|
Original
|
PDF
|
G2996
G2996
SSTL-18
|
Untitled
Abstract: No abstract text available
Text: G2996 Global Mixed-mode Technology Inc. DDR I/II Termination Regulator Features General Description The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR-SDRAM. It contains a high-speed operational
|
Original
|
PDF
|
G2996
G2996
SSTL-18
|
Untitled
Abstract: No abstract text available
Text: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM.
|
Original
|
PDF
|
UR5595
UR5595
QW-R502-062
|
LP2995M
Abstract: c151c LP2995 LP2995LQ LP2995LQX LP2995MR LP2995MRX LP2995MX M08A
Text: General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The
|
Original
|
PDF
|
LP2995
exte151°
LLP-16
100pF
LP2995
16-Lead
LQA16A
LP2995M
c151c
LP2995LQ
LP2995LQX
LP2995MR
LP2995MRX
LP2995MX
M08A
|
Untitled
Abstract: No abstract text available
Text: CM3202-02 DDR VDDQ and VTT Termination Voltage Regulator Product Description The CM3202−02 is a dual−output low noise linear regulator designed to meet SSTL−2 and SSTL−3 specifications for DDR−SDRAM VDDQ supply and termination voltage VTT supply.
|
Original
|
PDF
|
CM3202-02
CM3202â
|
LP2995
Abstract: LP2995LQ LP2995LQX LP2995M LP2995MR LP2995MRX LP2995MX M08A
Text: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The
|
Original
|
PDF
|
LP2995
LP2995
LP2995LQ
LP2995LQX
LP2995M
LP2995MR
LP2995MRX
LP2995MX
M08A
|
northbridge
Abstract: LP2995 LP2995LQ LP2995LQX LP2995M LP2995MX M08A
Text: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients.
|
Original
|
PDF
|
LP2995
LP2995
northbridge
LP2995LQ
LP2995LQX
LP2995M
LP2995MX
M08A
|
Untitled
Abstract: No abstract text available
Text: LP2998 LP2998 DDR-I and DDR-II Termination Regulator Literature Number: SNVS521G LP2998 DDR-I and DDR-II Termination Regulator General Description Features The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of
|
Original
|
PDF
|
LP2998
LP2998
SNVS521G
SSTL-18
|
Untitled
Abstract: No abstract text available
Text: IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE 14-BIT REGISTERED BUFFER WITH SSTL I/O IDT74SSTVF16857 FEATURES: DESCRIPTION: • • • • • • • • The SSTVF16857 is a 14-bit registered buffer designed for 2.3V-2.7V
|
Original
|
PDF
|
IDT74SSTVF16857
14-BIT
IDT74SSTVF16857
100mA
MIL-STD-883,
200pF,
SSTVF16857
310mV
|
SSTV16857
Abstract: No abstract text available
Text: IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16857 PRELIMINARY 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • • • 2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs
|
Original
|
PDF
|
IDT74SSTV16857
14-BIT
100mA
MIL-STD-883,
200pF,
SSTV16857
310mV
|
LP2994
Abstract: LP2994M LP2994MX M08A
Text: LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier
|
Original
|
PDF
|
LP2994
LP2994
CSP-9-111S2)
CSP-9-111S2.
LP2994M
LP2994MX
M08A
|
|
|
Untitled
Abstract: No abstract text available
Text: CM3202-02 DDR VDDQ and VTT Termination Voltage Regulator Product Description The CM3202−02 is a dual−output low noise linear regulator designed to meet SSTL−2 and SSTL−3 specifications for DDR−SDRAM VDDQ supply and termination voltage VTT supply.
|
Original
|
PDF
|
CM3202-02
CM3202-02/D
|
LP2995M
Abstract: LP2995MRX LP2995MX M08A LP2995 LP2995LQ LP2995LQX LP2995MR PSOP8
Text: General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The
|
Original
|
PDF
|
LP2995
CSP-9-111C2)
CSP-9-111S2)
LP2995M
LP2995MRX
LP2995MX
M08A
LP2995LQ
LP2995LQX
LP2995MR
PSOP8
|
LP2994
Abstract: LP2994M LP2994MX M08A
Text: LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier
|
Original
|
PDF
|
LP2994
LP2994
LP2994M
LP2994MX
M08A
|
CSPT857C
Abstract: IDT74SSTVF16857 SSTVF16857
Text: IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: IDT74SSTVF16857 DESCRIPTION: • • • • • • • • 2.3V to 2.7V Operation SSTL_2 Class I style data inputs/outputs
|
Original
|
PDF
|
IDT74SSTVF16857
14-BIT
100mA
MIL-STD-883,
200pF,
SSTVF16857
310mV
CSPT857C
IDT74SSTVF16857
|
SSTV16857
Abstract: IDT74SSTV16857
Text: IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • • • 2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs
|
Original
|
PDF
|
IDT74SSTV16857
14-BIT
100mA
MIL-STD-883,
200pF,
SSTV16857
310mV
IDT74SSTV16857
|
Untitled
Abstract: No abstract text available
Text: IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16857 PRELIMINARY 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • • • 2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs
|
Original
|
PDF
|
IDT74SSTV16857
14-BIT
100mA
MIL-STD-883,
200pF,
SSTV16857
310mV
|
Untitled
Abstract: No abstract text available
Text: IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16857 PRELIMINARY 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • • • 2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs
|
Original
|
PDF
|
IDT74SSTV16857
14-BIT
100mA
MIL-STD-883,
200pF,
SSTV16857
310mV
|
psop-8
Abstract: 8 lead psop-8 NS package num. mra08a resistor 0,15 Ohm 5W DATA SHEET psop 44 northbridge Op amp circuit applications SSTL-2 5041c free circuit diagram of motherboard SO-8
Text: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The
|
Original
|
PDF
|
LP2995
LP2995
CSP-9-111C2)
CSP-9-111S2)
CSP-9-111S2.
psop-8
8 lead psop-8 NS package num. mra08a
resistor 0,15 Ohm 5W DATA SHEET
psop 44
northbridge
Op amp circuit applications
SSTL-2
5041c
free circuit diagram of motherboard
SO-8
|
UR5595L
Abstract: UR5595L-SH2-R UR5595 UR5595-S08-R UR5595-SH2-R
Text: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM.
|
Original
|
PDF
|
UR5595
UR5595
QW-R502-062
UR5595L
UR5595L-SH2-R
UR5595-S08-R
UR5595-SH2-R
|
Untitled
Abstract: No abstract text available
Text: {¡J PERICOM PI3B3863 . 3.3V, 10-Bit, 2-Port BusSwitch with SSTL-2 Enable
|
OCR Scan
|
PDF
|
24-pin
PI3B3863
10-Bit,
PI3B3863
PS8167B
|
