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    SPIRENT COMMUNICATIONS Search Results

    SPIRENT COMMUNICATIONS Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    QE82527-G Rochester Electronics LLC QE82527 - CMOS COMMUNICATIONS CONTROLLER Visit Rochester Electronics LLC Buy
    MC6850/BJAJC Rochester Electronics LLC MC6850 - Asynchronous Communications Interface Adapter Visit Rochester Electronics LLC Buy
    MC68B50CP-G Rochester Electronics LLC MC68B50 - Asynchronous Communications Interface Adapter Visit Rochester Electronics LLC Buy
    MPC860TCVR50D4 Rochester Electronics LLC MPC860T - PowerQUICC, 32 Bit Power Architecture, 50MHz, Communications Processor, -40 to 95C Visit Rochester Electronics LLC Buy
    MPC860SRVR50D4 Rochester Electronics LLC MPC860SR - PowerQUICC, 32 Bit Power Architecture, 50MHz, Communications Processor, 0 to 95C Visit Rochester Electronics LLC Buy

    SPIRENT COMMUNICATIONS Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    OC-768

    Abstract: 84856M209 of optical fpgas xilinx virtex-II
    Text: SPIRENT COMMUNICATIONS SELECTS XILINX VIRTEX-II PLATFORM FPGAS . Page 1 of 2 FOR IMMEDIATE RELEASE SPIRENT COMMUNICATIONS SELECTS XILINX VIRTEX -II PLATFORM FPGAS FOR 40G OPTICAL TRANSPORT ANALYZER Most powerful Xilinx FPGAs provide competitive advantage


    Original     		PDF OC-768 84856M209) \esp\ccstories\spirent0283 84856M209 of optical fpgas xilinx virtex-II

    Untitled

    Abstract: No abstract text available
    Text: DLS 8100 VDSL Wireline Simulator S P E C I F I C AT I O N S The DLS 8100 is Spirent Communications DLS Systems latest wireline simulator. Designed specifically for testing VDSL equipment up to 30 MHz, the DLS 8100 is the only product on the market capable of providing the


    Original     		PDF 98-043R6)

    modem 8110

    Abstract: dls 5200
    Text: Spirent DLS 8110 VDSL Bridged Tap Simulator DLS 8110 Growing demand for high bandwidth multimedia applications with integrated voice, data and video is one of the primary drivers for VDSL technology, the natural evolution from ADSL. To assist data rate performance testing in VDSL chipset and modem


    Original     		PDF AX/4000 8110DLS0110 modem 8110 dls 5200

    AX4000

    Abstract: PM3388 DDR2 sodimm pcb layout
    Text: LatticeSCM SPI4.2 Interoperability with PMC-Sierra PM3388 August 2006 Technical Note TN1121 Introduction The System Packet Interface, Level 4, Phase 2 SPI4.2 is a system level interface, published in 2001 by the Optical Internetworking Forum (OIF), for packet and cell transfer between a physical layer (PHY) device and a link layer


    Original     		PDF PM3388 TN1121 OC-192 10Gbps PM-3388 PM-3388 1-800-LATTICE AX4000 PM3388 DDR2 sodimm pcb layout

    88E1111

    Abstract: 88E1118 88E1112 Marvell PHY 88E1118 Marvell PHY 88E1111 Datasheet Alaska Ultra 88E1111 Marvell PHY 88E1111 layout Marvell 88E1112 Marvell 88E1111 88e111
    Text: LatticeECP2M/Marvell Gigabit Ethernet Physical Layer Interoperability July 2007 Technical Note TN1163 Introduction This technical note describes a 1000BASE-X physical layer Gigabit Ethernet interoperability test between a LatticeECP2M device and the Marvell Alaska® Ultra 88E1111/ 88E1112 devices. The test was limited to the


    Original     		PDF TN1163 1000BASE-X 88E1111/ 88E1112 88E1111/88E1112 1-800-LATTICE 88E1111 88E1118 Marvell PHY 88E1118 Marvell PHY 88E1111 Datasheet Alaska Ultra 88E1111 Marvell PHY 88E1111 layout Marvell 88E1112 Marvell 88E1111 88e111

    88E1111

    Abstract: 88E1118 88E1112 sgmii specification ieee Marvell PHY 88E1111 Datasheet 88e111 Marvell PHY 88E1111 layout Marvell 88E1111 Marvell PHY 88E1118 88E1111 "mdio registers"
    Text: LatticeECP2M/Marvell Serial-GMII SGMII Physical Layer Interoperability November 2006 Technical Note TN1133 Introduction The Serial Gigabit Media Independent Interface (SGMII) is a connection bus for Ethernet MACs and PHYs defined by Cisco Systems. It replaces the classic 22-wire GMII connection with a low pin count, 4-pair, differential SGMII


    Original     		PDF TN1133 22-wire 10Mbps, 100Mbps 1000Mbps 88E1111/88E1112 1-800-LATTICE 88E1111 88E1118 88E1112 sgmii specification ieee Marvell PHY 88E1111 Datasheet 88e111 Marvell PHY 88E1111 layout Marvell 88E1111 Marvell PHY 88E1118 88E1111 "mdio registers"

    88E1111

    Abstract: Marvell PHY 88E1111 Datasheet Marvell PHY 88E1118 Marvell 88E1112 Marvell 88E1111 88E1118 Marvell PHY 88E1118 Datasheet Marvell PHY 88E1111 layout 88E1112 88e111
    Text: LatticeSC/Marvell Gigabit Ethernet Physical Layer Interoperability October 2008 Technical Note TN1120 Introduction The IEEE 802.3-2002 Gigabit Ethernet standard is organized along architectural lines, emphasizing the large-scale separation of the system into two parts: the Media Access Control MAC sub-layer of the Data Link Layer and the


    Original     		PDF TN1120 88E1111/88E1112 1-800-LATTICE 88E1112 88E1111 Marvell PHY 88E1111 Datasheet Marvell PHY 88E1118 Marvell 88E1112 Marvell 88E1111 88E1118 Marvell PHY 88E1118 Datasheet Marvell PHY 88E1111 layout 88e111

    88E1111

    Abstract: Marvell PHY 88E1111 Datasheet marvell 88E1111 register RGMII sgmii marvell 88E1118 Marvell PHY 88E1118 Marvell PHY 88E1111 layout Marvell 88E1112 88E1112 Marvell 88E1111
    Text: LatticeSC/Marvell Serial-GMII SGMII Physical Layer Interoperability November 2006 Technical Note TN1127 Introduction The Serial Gigabit Media Independent Interface (SGMII) is a connection bus for Ethernet MACs and PHYs defined by Cisco Systems. It replaces the classic 22-wire GMII connection with a low pin count, 4-pair, differential SGMII


    Original     		PDF TN1127 22-wire 10Mbps, 100Mbps 1000Mbps 88E1111/88E1112 1-800-LATTICE 88E1111 Marvell PHY 88E1111 Datasheet marvell 88E1111 register RGMII sgmii marvell 88E1118 Marvell PHY 88E1118 Marvell PHY 88E1111 layout Marvell 88E1112 88E1112 Marvell 88E1111

    IXF18101

    Abstract: IXF1810X intel FPGA
    Text: Lattice ORSPI4 / Intel IXF18101 Physical Layer Device Interoperability March 2004 Technical Note TN1059 Introduction The System Packet Interface Level 4, Phase 2 SPI4.2 , was defined by the Optical Internetworking Forum (OIF) as an interface for packet and cell transfers between a Physical Layer (PHY) device and a link layer device for applications requiring up to 10 Gbps aggregate bandwidth. Example applications include ATM, Packet over SONET/SDH,


    Original     		PDF IXF18101 TN1059 16-bit OC-192c IXF18101 IXF1810X intel FPGA

    MAX2769

    Abstract: Maxim MAX2769 SAW GPS GLONASS filter GPS chip max2769 APP4275 AN4275 GPS SAW filter active antenna 139dBm Universal Satellite Receiver Power Board Spirent Communications
    Text: Maxim > App Notes > WIRELESS, RF, AND CABLE Sep 15, 2008 Keywords: GPS, receiver chip, MAX2769, USB, LNA APPLICATION NOTE 4275 GPS USB Reference Design with the MAX2769 Abstract: The MAX2769 is a low-cost, single-conversion, low-IF frequency GPS receiver that provides 115dB cascaded gain and a 1.4dB cascaded NF.


    Original     		PDF MAX2769, MAX2769 MAX2769 115dB com/an4275 MAX2769: AN4275, APP4275, Maxim MAX2769 SAW GPS GLONASS filter GPS chip max2769 APP4275 AN4275 GPS SAW filter active antenna 139dBm Universal Satellite Receiver Power Board Spirent Communications

    str450

    Abstract: STR4500 ATR0635 UBLOX passive RF splitter ATR0610 car GPS cold amplifier avl using gps
    Text: Measuring GPS Sensitivity By Hans-Joachim Golberg, Head of GPS Development and Frank Gruson, GPS Product Line Manager Summary This document describes how to verify the important GPS parameters of acquisition and tracking sensitivity. Atmel Corporation • 2325 Orchard Parkway • San Jose, CA 95131


    Original     		PDF

    stm32f107

    Abstract: FX mode ethernet schematic optical ethernet schematic ST802RT1B Ethernet STM32F107 ST802RT1 28 MHZ crystal 100BASE-FX SMB200 STEVAL-PCC011V1
    Text: STEVAL-PCC011V1 ST802RT1B Ethernet PHY demonstration board Data brief Features • ST802RT1B fast Ethernet physical layer transceiver ■ On-board 3.3 V LDO regulator ■ On-board 25 MHz crystal ■ 12 jumpers for boot-strap configuration MII address, auto-negotiation, loopback, power


    Original     		PDF STEVAL-PCC011V1 ST802RT1B 20-pin STM32F107 40-pin SMB-200/ SMB-2000) stm32f107 FX mode ethernet schematic optical ethernet schematic Ethernet STM32F107 ST802RT1 28 MHZ crystal 100BASE-FX SMB200 STEVAL-PCC011V1

    loss tangent of FR4

    Abstract: Nelco 4000-13 AEL1001 40-001663 nelco SFP layout design Nelco-4000-13SI Nelco-4000 FR4 microstrip stub AEL10
    Text: PCB Layout Guidelines for Designing with Avago SFP+Transceivers Application Note 5362 Introduction Avago Technologies offers a broad portfolio of SFP+ solutions include SR, LR, and LRM variants operating up to 10.3125 Gb/s. As small form pluggable transceiver


    Original     		PDF 10Gb/s AEL1001 AV02-0725EN loss tangent of FR4 Nelco 4000-13 AEL1001 40-001663 nelco SFP layout design Nelco-4000-13SI Nelco-4000 FR4 microstrip stub AEL10

    stm32f107

    Abstract: stm32f107 usb ST802RT1A STM32F107 can Ethernet Ethernet STM32F107 st802rt1 STEVAL-PCC010V1 28 MHZ crystal Part-3 "ethernet PHY"
    Text: STEVAL-PCC010V1 ST802RT1A Ethernet PHY demonstration board with STM32F107 controller add-on board Data brief Features • ■ ST802RT1A Ethernet PHY demonstration board: – ST802RT1A fast Ethernet physical layer transceiver – On-board 3.3 V LDO regulator


    Original     		PDF STEVAL-PCC010V1 ST802RT1A STM32F107 20-pin 40pin SMB-200/ SMB-2000) stm32f107 usb STM32F107 can Ethernet Ethernet STM32F107 st802rt1 STEVAL-PCC010V1 28 MHZ crystal Part-3 "ethernet PHY"

    st802rt1

    Abstract: AFBR-5803Z stm32f107 MDC schottky diode ST AFBR-5803 nfe31pt222z1e9l AM00639 LD1117S33 STM32F107 can Ethernet FX mode ethernet schematic
    Text: UM0858 User manual Getting started with STEVAL-PCC011V1, ST802RT1 FX mode Ethernet PHY demonstration kit 1 Introduction The STEVAL-PCC011V1 demonstration kit was designed to evaluate the ST802RT1 FX mode. This device is a Fast Ethernet physical layer PHY interface which supports 100


    Original     		PDF UM0858 STEVAL-PCC011V1, ST802RT1 STEVAL-PCC011V1 STM32F107 AFBR-5803Z MDC schottky diode ST AFBR-5803 nfe31pt222z1e9l AM00639 LD1117S33 STM32F107 can Ethernet FX mode ethernet schematic

    st802rt1a

    Abstract: No abstract text available
    Text: STEVAL-PCC010V1 ST802RT1A Ethernet PHY demonstration board with STM32F107 controller add-on board Data brief Features • ST802RT1A Ethernet PHY demonstration board: – ST802RT1A fast Ethernet physical layer transceiver – On-board 3.3 V LDO regulator – On-board 25 MHz crystal


    Original     		PDF STEVAL-PCC010V1 ST802RT1A STM32F107 20-pin 40pin SMB-200/ SMB-2000)

    stm32f107

    Abstract: HFJ11-2477E J00-0086NL Typical RED, GREEN, YELLOW, AMBER GaAs LED HFJ11-2477E-L12 st802rt1 STM32F107 Flash programming BLM18BA05OSN1D stm32f107 usb H1300NL
    Text: UM0819 User manual Getting started with STEVAL-PCC010V1, ST802RT1 TX mode Ethernet PHY demonstration kit 1 Introduction The STEVAL-PCC010V1 demonstration kit was designed to evaluate the ST802RT1 TX mode. This device is a Fast Ethernet physical layer PHY interface which supports 100


    Original     		PDF UM0819 STEVAL-PCC010V1, ST802RT1 STEVAL-PCC010V1 STM32F107 HFJ11-2477E J00-0086NL Typical RED, GREEN, YELLOW, AMBER GaAs LED HFJ11-2477E-L12 STM32F107 Flash programming BLM18BA05OSN1D stm32f107 usb H1300NL

    Untitled

    Abstract: No abstract text available
    Text: Agilent N1960A GS-8800 Series 8960 Wireless Communication Design Verification (DV) and Conformance Test (CT) System Data Sheet N1960A A single platform test system • Accelerates design verification (DV) and conformance test (CT) • Supports GSM, GPRS, EGPRS,


    Original     		PDF N1960A GS-8800 N1960A DCS1800, cdma2000Â 5990-5805EN cdma2000

    USRobotics SPORTSTER

    Abstract: V.everything C54V90 Sportster ISDN Terry USRobotics courier SI2456 TIA793 TMS320C54V90 SPRA928
    Text: White Paper SPRA928 − July 2003 Network Model Coverage NMC Tests Terry Engel Mark Mattson TITAN Technology Alliance Texas Instruments ABSTRACT This paper discusses the standardization of the tests that are designed to evaluate analog and digital modems. Standardization allows users to compare modem performance easily


    Original     		PDF SPRA928 USRobotics SPORTSTER V.everything C54V90 Sportster ISDN Terry USRobotics courier SI2456 TIA793 TMS320C54V90

    Untitled

    Abstract: No abstract text available
    Text: Agilent E6701C GSM/GPRS Lab Application Data Sheet Use with the E5515B/C 8960 wireless communication test set and the E6785B GSM/GPRS/W-CDMA lab application to create your network on a bench E6701C GSM/GPRS Lab Application Functionality • Integrated GSM and GPRS


    Original     		PDF E6701C E5515B/C E6785B E6584A 5988-9683EN

    Marvell 88e1111 register map

    Abstract: 88E1111 88E1111 PHY registers map 88E1111 register map 88E1111 config 88E1111 registers Marvell PHY 88E1111 alaska register map Marvell PHY 88E1111 MDIO read write sfp Marvell 88E1111 application note Marvell PHY 88E111 alaska
    Text: LatticeECP3 Marvell SGMII Physical/MAC Layer Interoperability December 2009 Technical Note TN1197 Introduction This technical note describes an SGMII physical/MAC layer interoperability test between a LatticeECP3 device and the Marvell 88E1111 PHY. Specifically, the document discusses the following topics:


    Original     		PDF TN1197 88E1111 H0020 Marvell 88e1111 register map 88E1111 PHY registers map 88E1111 register map 88E1111 config 88E1111 registers Marvell PHY 88E1111 alaska register map Marvell PHY 88E1111 MDIO read write sfp Marvell 88E1111 application note Marvell PHY 88E111 alaska

    Marvell 88e1111 register map

    Abstract: 88E1111 config 88E1111 88E1111 PHY registers map 88E1111 register map 88E1111 registers 88E1111 jumbo 88E1111 GMII config Marvell PHY 88E1111 alaska register map 88E1112
    Text: LatticeECP3 Marvell 1 GbE 1000BASE-X Physical/MAC Layer Interoperability December 2009 Technical Note TN1196 Introduction This technical note describes a 1000BASE-X physical/MAC layer Gigabit Ethernet interoperability test between a LatticeECP3 device and the Marvell 88E1111 PHY.


    Original     		PDF 1000BASE-X) TN1196 1000BASE-X 88E1111 H0020 Marvell 88e1111 register map 88E1111 config 88E1111 PHY registers map 88E1111 register map 88E1111 registers 88E1111 jumbo 88E1111 GMII config Marvell PHY 88E1111 alaska register map 88E1112

    BDS Thread

    Abstract: SMB600 3300A SMB-600 MSC8122 MSC8144 MSC8144ADS MSC8144E MSC8144EC utfb
    Text: Freescale Semiconductor Application Note Document Number: AN3439 Rev. 0, 09/2007 MSC8144 Ethernet Performance Maximizing QUICC Engine Throughput by Andrew Temple NCSG DSP Applications Freescale Semiconductor, Inc. Austin, TX This application note explains how to configure and run


    Original     		PDF AN3439 MSC8144 MSC8144ADS) BDS Thread SMB600 3300A SMB-600 MSC8122 MSC8144ADS MSC8144E MSC8144EC utfb

    Untitled

    Abstract: No abstract text available
    Text: Agilent E6701D GSM/GPRS Lab Application Data Sheet For use with the E5515B/C 8960 wireless communication test Part of the Network on a Bench solution from Agilent The E6701D GSM/GPRS lab application gives R&D engineers a network emulator with RF measurement capability on their


    Original     		PDF E6701D E5515B/C E5515C 5989-0366EN