Tresos
Abstract: UM0565 SPI105 automotive ecu manual SPC563M SPI156 SPI DRIVER autosar autosar can driver
Text: UM0565 User manual SPC563M SPI driver Introduction This user manual describes the AUTOSAR serial peripheral interface SPI driver. AUTOSAR SPI driver configuration parameters and deviations from the specification are described in SPI driver chapter. AUTOSAR SPI driver requirements and APIs are described
|
Original
|
PDF
|
UM0565
SPC563M
Tresos
UM0565
SPI105
automotive ecu manual
SPI156
SPI DRIVER
autosar
autosar can driver
|
AT25DF1281
Abstract: 8MW1 VDFN AT45DBxxx atmel 528 8MW1 - VDFN footprint 8M1-A 8MA1 UDFN 8MW1 8S2 EIAJ SOIC 8cn3
Text: Density Vcc Min Mbits (V) DataFlash Page Erase Part Number Interface Architecture SPI SPI SPI SPI SPI SPI SPI, Rapid8 Speed (MHz) 66 66 66 66 66 66 66/50 Page-erase, Byte-alterable, 2.7 to 3.6V – Industrial Temperature Grade 2.7 2.7 2.7 2.7 2.7 2.7 2.7
|
Original
|
PDF
|
28-byte
AT25DF1281
8MW1 VDFN
AT45DBxxx
atmel 528
8MW1 - VDFN
footprint 8M1-A
8MA1 UDFN
8MW1
8S2 EIAJ SOIC
8cn3
|
JTAG MODULE SPI
Abstract: spi flash parallel port TSOP 28 SPI memory Package flash 88P8341
Text: SPI EXCHANGE SPI-3 TO SPI-4 Issue 1.0 FEATURES • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation - Maskable interrupts for fatal errors
|
Original
|
PDF
|
BH820-1)
88P8341
drw38
JTAG MODULE SPI
spi flash parallel port
TSOP 28 SPI memory Package flash
88P8341
|
IDT88P8344
Abstract: 88P8344
Text: SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 FEATURES • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation - Maskable interrupts for fatal errors
|
Original
|
PDF
|
BH820-1)
88P8344
IDT88P8344
88P8344
|
TSOP 48 thermal resistance type1
Abstract: IDT88P8342 drw22
Text: SPI EXCHANGE 2 x SPI-3 TO SPI-4 Issue 1.0 FEATURES • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation - Maskable interrupts for fatal errors
|
Original
|
PDF
|
BH820-1)
88P8342
TSOP 48 thermal resistance type1
IDT88P8342
drw22
|
AN1149
Abstract: NDS352P PIC18F14K50 PIC18F2321 PIC18F2331 USB-232
Text: USB-SPI TM Driver-free USB to synchronous serial SPI slave interface Mechanical Specifications Summary USB-SPI is a single chip USB to synchronous serial SPI slave interface. It greatly simplifies the connection of personal computer to a microcontroller capable of
|
Original
|
PDF
|
PIC18LF2455
PIC18F14K50
26-Aug-10
HW144-7
AN1149
NDS352P
PIC18F2321
PIC18F2331
USB-232
|
Untitled
Abstract: No abstract text available
Text: PRODUCT BRIEF IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 - Number of errors - Number of bytes FEATURES • • • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation
|
Original
|
PDF
|
IDT88P8341
800MHz
BH820-1)
88P8341
|
spi FIFO
Abstract: IDT88P8344 DSC-6370
Text: PRODUCT BRIEF IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4 - Number of errors - Number of bytes FEATURES • • • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation
|
Original
|
PDF
|
IDT88P8344
800MHz
BH820-1)
88P8344
spi FIFO
IDT88P8344
DSC-6370
|
spi on parallel port
Abstract: IDT88P8342
Text: PRODUCT BRIEF IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 - Number of errors - Number of bytes FEATURES • • • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation
|
Original
|
PDF
|
IDT88P8342
800MHz
BH820-1)
88P8342
6370a
spi on parallel port
IDT88P8342
|
xc6vlx130t-ff1156
Abstract: XILINX ipic axi
Text: LogiCORE IP AXI Serial Peripheral Interface AXI SPI (v1.02.a) DS742 January 18, 2012 Product Specification Introduction LogiCORE IP Facts The AXI Serial Peripheral Interface (SPI) connects to the Advanced eXtensible Interface (AXI4). This core provides a serial interface to SPI devices such as SPI
|
Original
|
PDF
|
DS742
M68HC11
32-bit
xc6vlx130t-ff1156
XILINX ipic axi
|
Untitled
Abstract: No abstract text available
Text: 0.1 MPC8XX I2C/SPI MICROCODE PACKAGE SPECIFICATIONS The modified I2C/SPI programming model allows concurrent operation of Ethernet and I2C or SPI by solving the parameter ram conflict caused by the fact that some of the Ethernet parameters overlay the I2C/SPI parameters. This is done by mapping the I2C/SPI parameters to other dual ported RAM area relocatable parameter ram .
|
Original
|
PDF
|
0x2202000
0x22021ff)
0x2202f00
0x2202fff)
|
25LC160
Abstract: DS464 M68HC11 MPC8260 M68HC11 reference manual ml300 ucf
Text: OPB Serial Peripheral Interface SPI (v1.00e) DS464 July 21, 2006 Product Specification 0 0 Introduction LogiCORE Facts The Xilinx OPB Serial Peripheral Interface (SPI) connects to the OPB and provides the controller interface to any SPI device such as SPI EEPROMs. It is
|
Original
|
PDF
|
DS464
M68HC11
M68HC11-Rev.
MPC8260
25LC160
M68HC11 reference manual
ml300 ucf
|
AVR151
Abstract: AVR910 SCK 104 avr spi ICE200 STK500
Text: AVR151: Setup And Use of The SPI Features • • • • • • • SPI Pin Functionality Multi Slave Systems SPI Timing SPI Transmission Conflicts Emulating the SPI Code examples for Polled operation Code examples for Interrupt Controlled operation 8-bit RISC
|
Original
|
PDF
|
AVR151:
2585C
AVR151
AVR910
SCK 104
avr spi
ICE200
STK500
|
AVR151
Abstract: AVR910 ICE200 STK500
Text: AVR151: Setup And Use of The SPI Features • • • • • • • SPI Pin Functionality Multi Slave Systems SPI Timing SPI Transmission Conflicts Emulating the SPI Code examples for Polled operation Code examples for Interrupt Controlled operation 8-bit RISC
|
Original
|
PDF
|
AVR151:
2585B
AVR151
AVR910
ICE200
STK500
|
|
|
Untitled
Abstract: No abstract text available
Text: ispLever CORE TM Quad SPI-3 to SPI-4 Link Layer Bridge Core User’s Guide October 2005 ipug29_02.0 Quad SPI-3 to SPI-4 Link Layer Bridge Core User’s Guide Lattice Semiconductor Introduction Lattice’s Quad SPI-3 System Packet Interface Level 3 to SPI-4 (System Packet Interface Level 4) Bridge is an IP
|
Original
|
PDF
|
ipug29
BS-2FE1036C.
SPI-324L-O4-N1.
|
Untitled
Abstract: No abstract text available
Text: Active Errata List • • • • During UART Reception, Clearing REN May Generate Unexpected IT SPI Interface - Transmission on Master Mode SPI Interface - SPI SS pin Limitation on Master/Slave SPI - SPI Slave Responding in a Multislave Configuration When Not Selected by the
|
Original
|
PDF
|
AT83C51IC2/T80C51ID2
|
AT80C51ID2
Abstract: spi slave atmel 8051 datasheet 80C51 AT80C51RD2 AT83C51RB2 AT83C51RC2 Atmel AT80 AT83C51IC2
Text: Active Errata List • • • • During UART Reception, Clearing REN May Generate Unexpected IT SPI Interface - Transmission on Master Mode SPI Interface - SPI SS pin Limitation on Master/Slave SPI - SPI Slave Responding in a Multislave Configuration When Not Selected by the
|
Original
|
PDF
|
AT83C51IC2/T80C51ID2
4242B
AT80C51ID2
spi slave
atmel 8051 datasheet
80C51
AT80C51RD2
AT83C51RB2
AT83C51RC2
Atmel AT80
AT83C51IC2
|
M95512 diagram
Abstract: M95512-DR M95512-W M95512 M95512-R
Text: M95512-DR M95512-R M95512-W 512 Kbit serial SPI bus EEPROM with high-speed clock Features • Compatible with SPI bus serial interface Positive clock SPI modes : – M95512-W and M95512-R: standard SPI 512 Kbit EEPROM – M95512-DR: standard SPI 512 Kbit
|
Original
|
PDF
|
M95512-DR
M95512-R
M95512-W
M95512-W
M95512-R:
M95512-DR:
M95512 diagram
M95512-DR
M95512
|
Untitled
Abstract: No abstract text available
Text: M95512-DR M95512-R M95512-W 512 Kbit serial SPI bus EEPROM with high-speed clock Features • Compatible with SPI bus serial interface Positive clock SPI modes : – M95512-W and M95512-R: standard SPI 512 Kbit EEPROM – M95512-DR: standard SPI 512 Kbit
|
Original
|
PDF
|
M95512-DR
M95512-R
M95512-W
M95512-W
M95512-R:
M95512-DR:
|
M95512
Abstract: M95512-DR M95512-R M95512-W
Text: M95512-DR M95512-R M95512-W 512 Kbit serial SPI bus EEPROM with high-speed clock Features • Compatible with SPI bus serial interface Positive clock SPI modes : – M95512-W and M95512-R: standard SPI 512 Kbit EEPROM – M95512-DR: standard SPI 512 Kbit
|
Original
|
PDF
|
M95512-DR
M95512-R
M95512-W
M95512-W
M95512-R:
M95512-DR:
M95512
M95512-DR
|
lps 256
Abstract: No abstract text available
Text: PRODUCT BRIEF IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 To request the full IDT88P8341 datasheet, please contact your local IDT Sales Representative or call 1-800-345-7015, you may also email SPI@idt.com FEATURES • • • Functionality - Low speed to high speed SPI exchange device
|
Original
|
PDF
|
IDT88P8341
IDT88P8341
BH820-1)
88P8341
drw38
lps 256
|
EEPROM ST M95256
Abstract: M95256-DR
Text: M95256-DR M95256 M95256-W M95256-R 256 Kbit serial SPI bus EEPROM with high-speed clock Features • Compatible with SPI bus serial interface positive clock SPI modes : – M95256, M95256-W and M95256-R: standard SPI 256 Kbit EEPROM – M95256-DR: standard SPI 256 Kbit
|
Original
|
PDF
|
M95256-DR
M95256
M95256-W
M95256-R
M95256,
M95256-R:
M95256-DR:
M95256
M95256-W
EEPROM ST M95256
|
Untitled
Abstract: No abstract text available
Text: RS232 & USB to SPI RS232/USB-SPI-N Bi-Directional Converter: RS232<->SPI or USB<->SPI The Big Deal • Allows Bi-Directional communication between USB or RS232 to SPI • Easy-to-use, quick-loading GUI and API objects for programmers - compatible with 32/64 Bit operating systems
|
Original
|
PDF
|
RS232
RS232/USB-SPI-N
RS232
LK1579
RS232/USB-SPI-N
330kbit/sec
|
Untitled
Abstract: No abstract text available
Text: RS232 & USB to SPI RS232/USB-SPI Bi-Directional Converter: RS232<->SPI or USB<->SPI The Big Deal • Allows Bi-Directional communication between USB or RS232 to SPI • Easy-to-use, quick-loading GUI and API objects for programmers - compatible with 32/64 Bit operating systems
|
Original
|
PDF
|
RS232
RS232/USB-SPI
RS232
LK1578
RS232/USB-SPI
330kbit/sec
|
