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    R4000

    Abstract: R4640 R4650 R4700 R5000 RM5230TM R5000 mips MIPS RM5230
    Text: RM5230 Superscalar Microprocessor with 32-Bit System Bus FEATURES • Dual Issue superscalar microprocessor — 100, 133, 150 and 175 MHz operating frequencies — 210 Dhrystone2.1 MIPS — SPECInt95 3.5, SPECfp95 3.7 • System interface optimized for embedded applications


    Original     		PDF RM5230TM 32-Bit SPECInt95 SPECfp95 RM5230-DS0011409910 R4000 R4640 R4650 R4700 R5000 R5000 mips MIPS RM5230

    microprocessor

    Abstract: G172
    Text: PC755/745 PowerPC 755/745 RISC Microprocessor Datasheet Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745)


    Original     		PDF PC755/745 1SPECint95, SPECfp95 PC755) 7SPECint95, 9SPECfp95 PC745) 64-bit microprocessor G172

    0828H

    Abstract: No abstract text available
    Text: PC755/745 PowerPC 755/745 RISC Microprocessor Datasheet Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745)


    Original     		PDF PC755/745 1SPECint95, SPECfp95 PC755) 7SPECint95, 9SPECfp95 PC745) 64-bit 0828H

    cga motorola

    Abstract: PowerPC755 PC755B 2138F CBGA360 MPC7400 PC745 PC755 PCX755
    Text: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)


    Original     		PDF 1SPECint95, SPECfp95 PC755) 7SPECint95, 9SPECfp95 PC745) 64-bit 32-bit cga motorola PowerPC755 PC755B 2138F CBGA360 MPC7400 PC745 PC755 PCX755

    2138F

    Abstract: CBGA360 MPC7400 PC745 PC755 ATMEL 745 PCX755
    Text: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)


    Original     		PDF 1SPECint95, SPECfp95 PC755) 7SPECint95, 9SPECfp95 PC745) 64-bit 32-bit 2138F CBGA360 MPC7400 PC745 PC755 ATMEL 745 PCX755

    21264

    Abstract: No abstract text available
    Text: Alpha 21264 DIGITAL Semiconductor Alpha 21264 Microprocessor Product Brief The Alpha 21264 microprocessor, with benchmarks over 30 SPECint95 and 50 SPECfp95, and with spectacular bandwidths over 4 GB/s for L2 cache TM and over 2 GB/s for memory, enables the system designer to produce the


    Original     		PDF SPECint95 SPECfp95, 64-bit 21264

    hall sensor u18 032

    Abstract: CBGA360 MPC7400 PC745B PC755B CBGA-255 atmel 0820 PowerPC755B
    Text: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755B 15.7SPECint95, SPECfp95 at 350 MHz (PC745B) 733 MIPS at 400 MHz (PC755B) at 641 MIPS at 350 MHz (PC745B) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)


    Original     		PDF 1SPECint95, SPECfp95 PC755B) 7SPECint95, 9SPECfp95 PC745B) 64-bit 32-bit hall sensor u18 032 CBGA360 MPC7400 PC745B PC755B CBGA-255 atmel 0820 PowerPC755B

    mips r5000

    Abstract: R5000 mips mips R5000 nec
    Text: MIPS R5000 Microprocessor Technical Backgrounder Performance: SPECint95 5.5 SPECfp95 5.5 Instruction Set MIPS-IV ISA Compatibility MIPS-I, MIPS-II, AND MIPS-III Pipeline Clock 200 MHz System Interface clock Up to 100 MHz Caches 32 kB I-cache and 32 kB D-cache, each 2-way set associative


    Original     		PDF R5000 SPECint95 SPECfp95 272-pin 223-pin R4000, R4400 32-bit 64-bit mips r5000 R5000 mips mips R5000 nec

    MIPS RM5231

    Abstract: RM5231-150Q R4000 R4650 R4700 R5000 RM5231
    Text: RM5231 Superscalar Microprocessor with 64-Bit System Bus FEATURES • Dual Issue superscalar microprocessor — 150, 200, 225, & 250 MHz operating frequencies — 300 Dhrystone2.1 MIPS — SPECInt95 5.0, SPECfp95 5.25 • System interface optimized for embedded applications


    Original     		PDF RM5231TM 64-Bit SPECInt95 SPECfp95 32-bit RM5231-DS0011209910 MIPS RM5231 RM5231-150Q R4000 R4650 R4700 R5000 RM5231

    21264

    Abstract: video server 130C samsung dvd power supply
    Text: PRODUCT BRIEF Alpha 21264 Microprocessor The Alpha 21264 microprocessor, with benchmarks over 30 SPECint95 and 50 SPECfp95, and with spectacular bandwidths over 3.2 GB/s for L2 cache and over 2.6 GB/s for memory, enables the system designer to produce the highest performance systems ranging from workstations to


    Original     		PDF SPECint95 SPECfp95, 21264 video server 130C samsung dvd power supply

    Untitled

    Abstract: No abstract text available
    Text: Features • • • • • • • • • • • • • • • 12.4 SPECint95, 8.4 SPECfp95 at 266 MHz TSPC750A with 1 MB L2 at 133 MHz 11.5 SPECint95, 6.9 SPECfp95 at 266 MHz (TSPC740A) 488 MIPS at 266 MHz Selectable Bus Clock (11 CPU Bus Dividers up to 8x)


    Original     		PDF SPECint95, SPECfp95 TSPC750A) TSPC740A) 64-bit 32-bit TSPC750Ab

    shmoo plot analysis

    Abstract: bit-slice PA-7100LC PA7100LC ieee paper on alu ISSCC-96 PA7100
    Text: IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 11, NOVEMBER 1996 1697 A 64-b Quad-Issue CMOS RISC Microprocessor Neela Gaddis and Jonathan Lotz Abstract— The HP-PA8000 is a 180-MHz quad-issue custom VLSI implementation of the HP-PA 2.0 64-b architecture delivering 11.84 SPECint95 and 20.18 SPECfp95 with 3.8 million


    Original     		PDF HP-PA8000 180-MHz SPECint95 SPECfp95 56-entry PA-8000 PA-7000 PA-7100, PA-7100LC, shmoo plot analysis bit-slice PA-7100LC PA7100LC ieee paper on alu ISSCC-96 PA7100

    MQUAD

    Abstract: PowerPC-603e 603E
    Text: Features H H H H H H H H 5.6 SPECint95, 4.0 SPECfp95 @ 200 MHz estimated Superscalar (3 instructions per clock peak). Dual 16KB caches. Selectable bus clock. 32-bit compatibility PowerPC implementation. On chip debug support. PD typical = 2.5 Watts (200 MHz), full operating conditions.


    Original     		PDF SPECint95, SPECfp95 32-bit PID7t-603e PowerPC603e TSPC603r MQUAD PowerPC-603e 603E

    PC8240

    Abstract: microprocessor TO-66 CASE OVDD10 2600 corning AD17 AE15 silicone grease 367 PCX8240
    Text: Features • 6.6 SPEC int 95, 5.5 SPECfp95 at 266 MHz Estimated • Superscalar 603e Core • Integer Unit (IU), Floating-Point Unit (FPU) (User Enabled or Disabled), Load/Store Unit • • • • • • • • • • (LSU), System Register Unit (SRU), and a Branch Processing Unit (BPU)


    Original     		PDF SPECfp95 16-Kbyte 32-bit PC8240 microprocessor TO-66 CASE OVDD10 2600 corning AD17 AE15 silicone grease 367 PCX8240

    PBGA255

    Abstract: 25X25 PowerPC755
    Text: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)


    Original     		PDF 1SPECint95, SPECfp95 PC755) 7SPECint95, 9SPECfp95 PC745) 64-bit 32-bit PBGA255 25X25 PowerPC755

    TSPC603

    Abstract: TSPC603R
    Text: Features • • • • • • • • • • • • • • • • • 7.4 SPECint95, 6.1 SPECfp95 at 300 MHz estimated Superscalar (3 instructions per clock peak) Dual 16 KB Caches Selectable Bus Clock 32-bit Compatibility PowerPC Implementation On-chip Debug Support


    Original     		PDF SPECint95, SPECfp95 32-bit 64-bit TSPC603 TSPC603R

    PLL VCO MIL-PRF-38535

    Abstract: TSPC603R D-H19 msr 206 pinout
    Text: Features • • • • • • • • 5.6 SPECint95, 4 SPECfp95 and 200 MHz Estimated Superscalar (3 Instructions per Clock Peak) Dual 16 KB Caches Selectable Bus Clock 32-bit Compatibility PowerPC Implementation On-Chip Debug Support PD Typically = 2.5W (200 MHz), Full Operating Conditions


    Original     		PDF SPECint95, SPECfp95 32-bit PID7t-603e PLL VCO MIL-PRF-38535 TSPC603R D-H19 msr 206 pinout

    logic diagram of johnson and ring counter

    Abstract: Loctite 819 Loctite 640 AD17 PC8240 Atmel LOT marking PCX8240 Loctite 576
    Text: Features H 6.6 SPEC int 95, 5.5 SPECfp95 @ 266 MHz estimated H Superscalar 603e core H Integer unit (IU), floating-point unit (FPU) (user enabled or disabled), load/ store unit (LSU), system register unit (SRU), and a branch processing unit (BPU). H 16-Kbyte instruction cache


    Original     		PDF SPECfp95 16-Kbyte PC8240 32-bit PC8240 logic diagram of johnson and ring counter Loctite 819 Loctite 640 AD17 Atmel LOT marking PCX8240 Loctite 576

    Untitled

    Abstract: No abstract text available
    Text: PC8240 Integrated Processor Family Datasheet - Preliminary Specification Features • 6.6 SPEC int 95, 5.5 SPECfp95 at 266 MHz Estimated • Superscalar 603e Core • Integer Unit (IU), Floating-Point Unit (FPU) (User Enabled or Disabled), Load/Store Unit (LSU), System Register Unit (SRU),


    Original     		PDF PC8240 SPECfp95 16-Kbyte 32-bit MHz42 0885Câ

    cga motorola

    Abstract: CBGA360 MPC7400 PC745 PC755 N-19 CI-CGA360 PowerPC755
    Text: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)


    Original     		PDF 1SPECint95, SPECfp95 PC755) 7SPECint95, 9SPECfp95 PC745) 64-bit 32-bit cga motorola CBGA360 MPC7400 PC745 PC755 N-19 CI-CGA360 PowerPC755

    atmel 528 24 c01

    Abstract: TSPC603R
    Text: Features • • • • • • • • • • • • • • • • • 7.4 SPECint95, 6.1 SPECfp95 at 300 MHz Estimated Superscalar (3 Instructions per Clock Peak) Dual 16 KB Caches Selectable Bus Clock 32-bit Compatibility PowerPC Implementation On-chip Debug Support


    Original     		PDF SPECint95, SPECfp95 32-bit 64-bit PID7t-603e 2125B atmel 528 24 c01 TSPC603R

    BERG CONNECTOR

    Abstract: No abstract text available
    Text: PC755/745 PowerPC 755/745 RISC Microprocessor Datasheet Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745)


    Original     		PDF PC755/745 1SPECint95, SPECfp95 PC755) 7SPECint95, 9SPECfp95 PC745) 64-bit BERG CONNECTOR

    Untitled

    Abstract: No abstract text available
    Text: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)


    Original     		PDF 1SPECint95, SPECfp95 PC755) 7SPECint95, 9SPECfp95 PC745) 64-bit 32-bit

    ATMEL 745

    Abstract: PCX755 PC755B CBGA360 MPC7400 PC745 PC755 PCX745 PC745 PBGA255 C PBGA255
    Text: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)


    Original     		PDF 1SPECint95, SPECfp95 PC755) 7SPECint95, 9SPECfp95 PC745) 64-bit 32-bit ATMEL 745 PCX755 PC755B CBGA360 MPC7400 PC745 PC755 PCX745 PC745 PBGA255 C PBGA255