SONET TESTBENCH Search Results

SONET TESTBENCH Result Highlights (5)

Part	Manufacturer	Description
M1061-11I155.5200T	Renesas Electronics Corporation	VCSO FEC PLL For SONET/OTN
M2065-11-669.3266	Renesas Electronics Corporation	VCSO FEC PLL For SONET/OTN
M2061-11-622.0800T	Renesas Electronics Corporation	VCSO FEC PLL For SONET/OTN
M1060-11I166.6286	Renesas Electronics Corporation	VCSO FEC PLL For SONET/OTN
M2061-11I622.0800	Renesas Electronics Corporation	VCSO FEC PLL For SONET/OTN

SONET TESTBENCH Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
vhdl code for dice game Abstract: Video Proc 3.3V 0.07A 64-Pin PQFP ez811 GRAPHICAL LCD interfaced with psoc 5 cypress ez-usb AN2131QC CYM9239 vhdl code PN 250 code generator CY3649 cy7c63723 Keyboard and Optical mouse program CY7C9689 ethernet Text: Product Selector Guide Communications Products Description Pins Part Number Freq. Range Mbps ICC (mA) Packages* 3.3V SONET/SDH PMD Transceiver 2.5V SiGe Low Power SONET/SDH Transceiver SONET/SDH Transceiver w/ 100K Logic 2.5 G-Link w/ 100K Logic OC-48 Packet Over SONET (POS) Framer	Original	OC-48 CYS25G0101DX CYS25G0102 CYS25G01K100 CYP25G01K100 CY7C9536 CY7C955 CY7B952 CY7B951 10BASE vhdl code for dice game Video Proc 3.3V 0.07A 64-Pin PQFP ez811 GRAPHICAL LCD interfaced with psoc 5 cypress ez-usb AN2131QC CYM9239 vhdl code PN 250 code generator CY3649 cy7c63723 Keyboard and Optical mouse program CY7C9689 ethernet	PDF
512Kx32x4 Abstract: vhdl GPCM TADM042G5 block diagram 8085 microprocessor based traffic control system Text: Preliminary Data Sheet November 2001 Quad-Port Gigabit Ethernet Over SONET/SDH Smart Silicon Solution Features Overview • Encapsulates GbE frames into the SONET/SDH protocol using packet-over-SONET POS format. ■ Support for jumbo Ethernet packets (9.6 kbytes in	Original	DS02-055NCIP DS01-230NCIP) 512Kx32x4 vhdl GPCM TADM042G5 block diagram 8085 microprocessor based traffic control system	PDF
TADM042G5 Abstract: dual y34 sim data LG1627BXC TDAT042G5 TRCV012G5 TTRN012G5 DS01001 an30 laser Text: Advance Data Sheet November 2000 Dual-Gigabit Ethernet Over SONET/SDH Smart Silicon Solution Overview The dual-gigabit Ethernet GbE over SONET/SDH design is a system solution for transporting GbE frames over existing SONET/SDH rings or point-topoint connections. It is provided using a combination	Original	DS01-001NCIP TADM042G5 dual y34 sim data LG1627BXC TDAT042G5 TRCV012G5 TTRN012G5 DS01001 an30 laser	PDF
sonet testbench Abstract: CP155 GR-253-CORE Text: SONET STS-1 Framer MegaCore Function STS1FRM June 2001; ver. 1.01 Data Sheet • Features ■ ■ ■ ■ ■ ■ Typical Applications Performs synchronous optical network (SONET) framing and transmission convergence (TC) Processes transport overhead (TOH) and path overhead (POH)	Original		PDF
CP622 Abstract: GR-253-CORE STS12CFRM Text: SONET/SDH STS-12c/STM-4 Framer MegaCore Function STS12CFRM July 2001; ver. 1.01 Data Sheet • Features ■ ■ ■ ■ ■ ■ Typical Applications Performs synchronous optical network (SONET)/synchronous digital hierarchy (SDH) framing and transport convergence (TC)	Original	STS-12c/STM-4 STS12CFRM) CP622 GR-253-CORE STS12CFRM	PDF
16 byte register VERILOG Abstract: verilog code BIP-8 GR-253 GR-253-CORE STS12CFRM digital alarm clock vhdl code in modelsim alarm clock design of digital VHDL Text: SONET/SDH STS-12c/STM-4 Framer MegaCore Function STS12CFRM July 2001 User Guide Version 1.01 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com A-UG-IPSTS12CFRM-1.01 SONET/SDH STS-12c/STM-4 Framer MegaCore Function (STS12CFRM) User Guide	Original	STS-12c/STM-4 STS12CFRM -UG-IPSTS12CFRM-1 STS-12c/STM-4 STS12CFRM) STS12c/STM-1 16 byte register VERILOG verilog code BIP-8 GR-253 GR-253-CORE STS12CFRM digital alarm clock vhdl code in modelsim alarm clock design of digital VHDL	PDF
vhdl code for stm-1 sequence Abstract: vhdl code for BIP-8 generator STM-1 verilog code BIP-8 rw0s ATM machine working circuit diagram using sonet vhdl 16 byte register VERILOG AIRbus Interface alarm clock design of digital VHDL vhdl code for 9 bit parity generator vhdl code stm-64 Text: SONET/SDH STS-3c/STM-1 Framer MegaCore Function STS3CFRM June 2001 User Guide Version 1.01 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com A-UG-IPSTS3CFRM-1.01 SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide	Original		PDF
verilog code BIP-8 Abstract: alarm clock verilog code rw0s digital alarm clock vhdl code in modelsim ATM machine working circuit diagram using sonet vhdl vhdl code for 1 bit error generator vhdl code for 9 bit parity generator GR-253 GR-253-CORE verilog implementation of sts1 pointer processing Text: SONET STS-3 Framer MegaCore Function STS1X3FRM June 2001 User Guide Version 1.01 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com A-UG-IPSTS1X3FRM-1.01 SONET STS-3 Framer MegaCore Function (STS1X3) User Guide Altera, APEX, APEX 20K, MegaCore, MegaWizard, OpenCore, Quartus, and Quartus II are trademarks and/or service marks of	Original		PDF
verilog implementation of sts1 pointer processing Abstract: verilog code BIP-8 GR-253 J0 byte length 14 GR-253 GR-253-CORE Text: SONET STS-1 Framer MegaCore Function STS1FRM June 2001 User Guide Version 1.01 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com A-UG-IPSTS1FRM-1.01 SONET STS-1 Framer MegaCore Function (STS1FRM) User Guide Altera, APEX, APEX 20K, MegaCore, MegaWizard, OpenCore, Quartus, and Quartus II are trademarks and/or service marks of	Original		PDF
vhdl spi interface Abstract: flexbus interface Text: New Products Cores New Flexbus-4 Core • Multiple data transfer modes, including: Packet-Over-SONET POS – POS mode transmits data formatted in variablelength packets A Seamless Solution for 10 Gbps Networking Applications Asynchronous Transfer Mode (ATM) –	Original		PDF
CP155 Abstract: No abstract text available Text: SONET STS-1 Framer MegaCore Function STS1FRM December 19, 2000; ver. 1.00 Features • ■ ■ ■ ■ ■ ■ Typical Applications Easy-to-use MegaWizard Plug-In generates MegaCore® variants QuartusTM software and OpenCoreTM feature allow place-and-route,	Original		PDF
BM1S Abstract: sonet testbench CP155 Text: SONET/SDH STS-3c/STM-1 Framer MegaCore Function STS3CFRM December 19, 2000; ver. 1.00 Features • ■ ■ ■ ■ ■ ■ Typical Applications Easy-to-use MegaWizard Plug-In generates MegaCore® variants QuartusTM software and OpenCoreTM feature allow place-and-route,	Original		PDF
GR-253-CORE Abstract: No abstract text available Text: SONET STS-3 Framer MegaCore Function STS1X3FRM June 2001; ver. 1.01 Features Data Sheet • ■ ■ ■ ■ ■ ■ Typical Applications Easy-to-use MegaWizard Plug-In generates MegaCore® variants Quartus® II software and OpenCore® feature allow place-and-route,	Original		PDF
CP155 Abstract: GR-253-CORE Text: SONET/SDH STS-3c/STM-1 Framer MegaCore Function STS3CFRM June 2001, ver. 1.01 Data Sheet • ■ Features ■ ■ ■ ■ ■ Typical Applications Easy-to-use MegaWizard Plug-In generates MegaCore® variants Quartus® II software and OpenCore® feature allow place-and-route,	Original		PDF

OTU1 Abstract: XIP2174 Paxonet Communications OC48 ISE4 OTN testbench Text: STS48 OTN Framer/Digital Wrapper CC381 July 9, 2002 Product Specification AllianceCORE Facts Provided with Core Documentation User Guide, Design Guide EDIF netlist Design File Formats Constraints File cc381.ucf Testbench, test scripts Verification Tool	Original	STS48 CC381) cc381 OTU1 XIP2174 Paxonet Communications OC48 ISE4 OTN testbench	PDF
OTN testbench Abstract: CC481 XIP2196 OTU2 framer OC48 STS192 XILINX vhdl code REED SOLOMON encoder decoder vhdl code for bram Generic AIS verilog code for TCM decoder Text: STS192 OTN Framer/Digital Wrapper CC481 July 9, 2002 Product Specification AllianceCORE Facts Provided with Core Documentation User Guide, Design Guide EDIF netlist Design File Formats Constraints File cc481.ucf Testbench, test scripts Verification Tool	Original	STS192 CC481) cc481 OTN testbench XIP2196 OTU2 framer OC48 XILINX vhdl code REED SOLOMON encoder decoder vhdl code for bram Generic AIS verilog code for TCM decoder	PDF
rx data path interface in vhdl Abstract: vhdl code for 8-bit calculator CRC-16 CRC-32 STS-48 CC226 x431 fpga vhdl code for crc-32 CRC-16 and verilog vhdl code for scrambler descrambler Text: CoreEl 1.25 Gb/s GFP Framer CC224 May 30, 2003 Product Specification AllianceCORE™ Facts Core Specifics See Table 1 Provided with Core Documentation CC224 Functional Specification Design File Formats EDIF netlist Constraints File .ucf Script Based Behavioral	Original	CC224) CC224 apCC224 rx data path interface in vhdl vhdl code for 8-bit calculator CRC-16 CRC-32 STS-48 CC226 x431 fpga vhdl code for crc-32 CRC-16 and verilog vhdl code for scrambler descrambler	PDF
fpga vhdl code for crc-32 Abstract: crc verilog code 16 bit verilog code for 10 gb ethernet verilog code for frame synchronization sonet testbench XC2VP20 vhdl code scrambler STM 64 FRAMER WITH OTN vhdl code stm-64 CRC-16 Text: CoreEl CC327 10Gb GFP Framer May 6, 2003 Product Specification AllianceCORE™ Facts Paxonet Communications, Inc. 4046 Clipper Court Fremont CA 94538, USA Phone: +1 510-770-2277 Fax: +1 510-770-2288 E-mail: sales@paxonet.com URL: www.paxonet.com Features	Original	CC327 OC-192 fpga vhdl code for crc-32 crc verilog code 16 bit verilog code for 10 gb ethernet verilog code for frame synchronization sonet testbench XC2VP20 vhdl code scrambler STM 64 FRAMER WITH OTN vhdl code stm-64 CRC-16	PDF
GR-253-CORE Abstract: No abstract text available Text: T3 Mapper MegaCore Function T3MAP February 20, 2001; ver. 1.00 • ■ Features ■ ■ ■ ■ ■ ■ ■ Typical Applications Data Sheet Easy-to-use MegaWizard Plug-In generates MegaCore® variants QuartusTMII software and OpenCoreTM feature allow place-androute, and static timing analysis of designs prior to licensing	Original		PDF
GR-253-CORE Abstract: synchronous fifo design in verilog Text: T3 Mapper MegaCore Function T3MAP February 20, 2001 User Guide Version 1.0 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com A-UG-IPT3MAPPER-1.0 T3 Mapper MegaCore Function (T3MAP) User Guide Altera, APEX, APEX 20K, APEX 20KE, MegaCore, MegaWizard, OpenCore, Quartus, and Quartus II are trademarks and/or	Original		PDF
OTU1 Abstract: AN-607-1 OC48 SONET OC48 Text: Dynamic Reconfiguration of Transceiver Channels Using Multiple PLLs in Stratix IV Dynamic Reconfiguration of Transceiver Channels Using Multiple PLLs in Stratix IV Devices AN-607-1.2 Application Note This application note describes how you can dynamically reconfigure your Stratix IV	Original	AN-607-1 OTU1 OC48 SONET OC48	PDF
vhdl code for ofdm transceiver using QPSK Abstract: soft 16 QAM modulation matlab code verilog code for ofdm transmitter dac 0808 interfacing with 8051 microcontroller vhdl code for ofdm transmitter VHDL PROGRAM for ofdm turbo codes matlab simulation program 16 QAM adaptive modulation matlab E1 pdh vhdl uart 16750 Text: Intellectual Property Selector Guide IP Functions for System-on-a-Programmable-Chip Solutions March 2003 Contents • Introduction to Altera IP Megafunctions Page 3 • DSP Solutions Page 5 • Communications Solutions Page 11 • Microsystems Solutions Page 16	Original	ARM922T vhdl code for ofdm transceiver using QPSK soft 16 QAM modulation matlab code verilog code for ofdm transmitter dac 0808 interfacing with 8051 microcontroller vhdl code for ofdm transmitter VHDL PROGRAM for ofdm turbo codes matlab simulation program 16 QAM adaptive modulation matlab E1 pdh vhdl uart 16750	PDF
RFC-1619 Abstract: foundation field bus protocol PLX9080 RFC1619 counter schematic diagram vhdl code CRC 32 vhdl code for scrambler descrambler VHDL CODE FOR HDLC controller Text: PPP8 HDLC Core CC318f November 23, 1998 C ooreEl MicroSystems CoreEl MicroSystems 46750 Fremont Blvd. #208 Fremont, CA 94538 USA Phone: +1 510-770-2277 Fax: +1 510-770-2288 URL: www.coreel.com E-mail: sales@coreel.com Features • • • • • • •	Original	CC318f) RFC1619 16/32-bit RFC-1619 foundation field bus protocol PLX9080 counter schematic diagram vhdl code CRC 32 vhdl code for scrambler descrambler VHDL CODE FOR HDLC controller	PDF
OTU2 framer Abstract: verilog code for TCM decoder 8 BIT PROCESSOR USING VHDL Text: CoreEl CC481 OTU2 Framer May 6, 2003 Product Specification AllianceCORE™ Facts separately Core Specifics See Table 1 Provided with Core Documentation User Guide, Design Guide EDIF netlist, NGC netlist Design File Formats Constraints Files cc481chp.ucf, cc481_wrap.ucf	Original	CC481 cc481chp OTU2 framer verilog code for TCM decoder 8 BIT PROCESSOR USING VHDL	PDF

SONET TESTBENCH Search Results

SONET TESTBENCH Result Highlights (5)

SONET TESTBENCH Datasheets Context Search

vhdl code for dice game

512Kx32x4

TADM042G5

sonet testbench

CP622

16 byte register VERILOG

vhdl code for stm-1 sequence

verilog code BIP-8

verilog implementation of sts1 pointer processing

vhdl spi interface

CP155

BM1S

GR-253-CORE

CP155

OTU1

OTN testbench

rx data path interface in vhdl

fpga vhdl code for crc-32

GR-253-CORE

GR-253-CORE

OTU1

vhdl code for ofdm transceiver using QPSK

RFC-1619

OTU2 framer