F628
Abstract: STS-192 STS-48
Text: 4. SONET Mode SGX52004-1.2 Introduction One of the most common serial backplanes in the communications or telecom area is the SONET/SDH interface. For SONET/SDH applications the synchronous transport signal STS-48 and Synchronous Transport Module -16 STM -16 are becoming popular SONET
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SGX52004-1
STS-48
STS-12/STS-48
STS-192
F628
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Untitled
Abstract: No abstract text available
Text: Cortina Systems LXT6155 155 Mbps SDH/SONET/ATM Transceiver Datasheet The Cortina Systems® LXT6155 155 Mbps SDH/SONET/ATM Transceiver LXT6155 Transceiver is a high speed fully integrated transceiver designed for 155 Mbps SDH/SONET/ATM transmission system
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LXT6155
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LXT6155
Abstract: frequency doubler LXT6155LE
Text: Cortina Systems LXT6155 155 Mbps SDH/SONET/ATM Transceiver Datasheet The Cortina Systems® LXT6155 155 Mbps SDH/SONET/ATM Transceiver LXT6155 Transceiver is a high speed fully integrated transceiver designed for 155 Mbps SDH/SONET/ATM transmission system
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LXT6155
frequency doubler
LXT6155LE
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LXT6155LE
Abstract: LXT6155 GR-253 RG59U cortina cs Application Note document number 249280 G.703 standard - quad E1 interface
Text: Cortina Systems LXT6155 155 Mbps SDH/SONET/ATM Transceiver Datasheet The Cortina Systems® LXT6155 155 Mbps SDH/SONET/ATM Transceiver LXT6155 Transceiver is a high speed fully integrated transceiver designed for 155 Mbps SDH/SONET/ATM transmission system
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LXT6155
LXT6155LE
GR-253
RG59U
cortina cs
Application Note document number 249280
G.703 standard - quad E1 interface
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IC E3 F6
Abstract: GR-253 XRT94L43
Text: XRT94L43 SONET/SDH OC-12 TO 12XDS3/E3 MAPPER NOVEMBER 2006 GENERAL DESCRIPTION The XRT94L43 is an SDH to PDH physical layer processor with integrated SONET OC-12 and 12 DS3/E3 framing controller. The XRT94L43 contains an integral SONET framer which provides framing
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XRT94L43
OC-12
12XDS3/E3
XRT94L43
STS-12/STM-4
IC E3 F6
GR-253
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Untitled
Abstract: No abstract text available
Text: DATA SHEET Communications T3/STS-1/E3 EVALUATION MANUAL XRT7295 DS3/Sonet STS-1 Integrated Line Receiver The XR-T7295 DS3/SONET STS-1 integrated line receiver is a fully integrated receive interface that terminates a bipolar DS3 44.736Mbps or Sonet STS-1 (51.84Mbps) signal
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XRT7295
XR-T7295
736Mbps)
84Mbps)
450ft.
20-pin
XR-T7295,
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Untitled
Abstract: No abstract text available
Text: SY69712 SONET/SDH/ATM S ip e r COM h'w in.’i O C - 1 2 C lo ck R e c o v e r in g T r a n s c e iv e r • A complete SONET/SDH Transmitter & Receiver ■ SONET 622.08Mbtt/sec data rates OC-12 SY69612 SONET/SDH/ATM OC-12 ■ Complies with Bellcore, CCITT and ANSI
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SY69712
08Mbtt/sec
OC-12)
44MHz,
84MHz
76MHz
100-pin
SY877Q1V
50Mbps
X3T12
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MPC860 jtag
Abstract: IBM 236 telecom bus
Text: XRT94L43 SONET/SDH OC-12 TO 12XDS3/E3 MAPPER NOVEMBER 2006 GENERAL DESCRIPTION The XRT94L43 is an SDH to PDH physical layer processor with integrated SONET OC-12 and 12 DS3/E3 framing controller. The XRT94L43 contains an integral SONET framer which provides framing
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XRT94L43
OC-12
12XDS3/E3
XRT94L43
STS-12/STM-4
inter/STS-12
516-ball
MPC860 jtag
IBM 236
telecom bus
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Untitled
Abstract: No abstract text available
Text: w Fw ip XR-T7295 —ihe analog plus company April 1994-3 DS3 / SONET STS-1 Integrated Line Receiver GENERAL DESCRIPTION PIN ASSIGNMENT The XR-T7295 DS3/SONET STS-1 integrated line receiver is a fully integrated receive interface that ter minates a bipolar DS3 44.736 MBPS or SONET
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XR-T7295
XR-T7295
3422blÃ
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GR-253
Abstract: GR-253-CORE GR-499-CORE XRT75L00D XRT75L00DIV XRT75L03 ANSI T1.105.03B 1997 CI 9821 ST CHN 703 chn 347
Text: XRT75L00D E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER FEBRUARY 2004 REV. 1.0.2 • On-chip clock synthesizer provides the appropriate GENERAL DESCRIPTION The XRT75L00D is a single-channel fully integrated Line Interface Unit LIU with Sonet Desynchronizer
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XRT75L00D
XRT75L00D
GR-253
GR-253-CORE
GR-499-CORE
XRT75L00DIV
XRT75L03
ANSI T1.105.03B 1997
CI 9821
ST CHN 703
chn 347
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75l00d
Abstract: No abstract text available
Text: áç XRT75L00D E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER NOVEMBER 2003 REV. 1.0.1 • On-chip clock synthesizer provides the appropriate GENERAL DESCRIPTION The XRT75L00D is a single-channel fully integrated Line Interface Unit LIU with Sonet Desynchronizer
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XRT75L00D
XRT75L00D
75l00d
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JA02
Abstract: ana 608 GR-253 GR-253-CORE GR-499-CORE XRT75L04D XRT75L04DIV chn 347
Text: áç XRT75L04D FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER NOVEMBER 2003 GENERAL DESCRIPTION The XRT75L04D is a four-channel fully integrated Line Interface Unit LIU with Sonet Desynchronizer for E3/DS3/STS-1 applications. It incorporates four
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XRT75L04D
XRT75L04D
JA02
ana 608
GR-253
GR-253-CORE
GR-499-CORE
XRT75L04DIV
chn 347
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Untitled
Abstract: No abstract text available
Text: DS3181/DS3182/DS3183/DS3184 Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIU www.maxim-ic.com GENERAL DESCRIPTION DS3/E3/STS-1 PORTS APPLICATIONS Access Concentrators SONET/SDH ADM SONET/SDH Muxes PBXs Digital Cross Connect Test Equipment Routers and Switches
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DS3181/DS3182/DS3183/DS3184
DS3181
DS3181N
DS3182
DS3182N
DS3183
DS3183N
DS3184
DS3184N
DS318x
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XR-T7295SOJ
Abstract: T1102A
Text: XR-T7295 DS31SONET STS-1 Integrated Line Receiver PIN ASSIGNMENT GENERAL DESCRIPTION The XR-T7295 DS3/SONET STS-1 Integrated Line Receiver is a fully integrated receive interface that terminates a bipolar DS3 44.736 MBPS or SONET (51.84 MBPS) signal transmitted over coaxial cable.
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XR-T7295
DS31SONET
450ft.
XR-T7295SOJ
T1102A
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T85 Slide Switch
Abstract: HP SLM MCP860 vt6 transistor 49Mhz power amplifier AU-AIS i860 64-Bit Microprocessor Performance Brief LTE DL Channel Encoder transformer e19 working of 5 pin relay t73
Text: XRT86SH328 SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND ARCHITECTURE DESC AUGUST 2008 REV. 1.0.1 GENERAL DESCRIPTION The XRT86SH328 Voyager is a physical layer SONET/SDH to PDH mapper/demapper which enables T1/E1 aggregation to STS-3/STM-1 or STS1/
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XRT86SH328
28-T1/21-E1
VC-11/VC-12
T85 Slide Switch
HP SLM
MCP860
vt6 transistor
49Mhz power amplifier
AU-AIS
i860 64-Bit Microprocessor Performance Brief
LTE DL Channel Encoder
transformer e19
working of 5 pin relay t73
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T7295
Abstract: t7295-3
Text: Data Sheet February 1997 microelectronics group Lucent Technologies Bell Labs Innovations T7295-6 DS3/SONET STS-1 Integrated Line Receiver Features Description • Fully integrated receive interface supports both DS3 and STS-1 rate signals The T7295-6 DS3/SONET STS-1 Integrated Line
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T7295-6
TR-NWT000499,
T7295-3
T7295-5
DS97-038TIC
DS94-196TIC)
T7295
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chn 752
Abstract: HDB3 CODING DECODING FPGA chn 501 chn 732
Text: XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER OCTOBER 2003 REV. 1.0.2 GENERAL DESCRIPTION attenuators can be used for clock smoothing in SONET STS-1 to DS-3 de-mapping. The XRT75L06D is a six channel fully integrated Line
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XRT75L06D
XRT75L06D
chn 752
HDB3 CODING DECODING FPGA
chn 501
chn 732
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CHN 523
Abstract: HDB3 CODING DECODING FPGA chn 752 chn 751 chn 720 GR-253 GR-253-CORE GR-499-CORE XRT75L06D XRT75L06DIB
Text: xr XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER APRIL 2005 REV. 1.0.4 GENERAL DESCRIPTION attenuators can be used for clock smoothing in SONET STS-1 to DS-3 de-mapping. The XRT75L06D is a six channel fully integrated Line
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XRT75L06D
XRT75L06D
CHN 523
HDB3 CODING DECODING FPGA
chn 752
chn 751
chn 720
GR-253
GR-253-CORE
GR-499-CORE
XRT75L06DIB
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G703S
Abstract: DSX-3 LTA 703 S
Text: JTEXAR XR-T7295 DS3 1SONET STS-1 Integrated Line Receiver GENERAL DESCRIPTION PIN ASSIGNMENT The XR-T7295 DS3/SONET STS-1 Integrated Line Receiver is a fully integrated receive interface that terminates a bipolar DS3 44.736 MBPS or SONET (51.84 MBPS) signal transmitted over coaxial cable.
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XR-T7295
XR-T7295
450ft.
G703S
DSX-3
LTA 703 S
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Untitled
Abstract: No abstract text available
Text: PHAST-48V Device STM-16/OC-48 SDH/SONET Overhead Terminator and Virtual Tributary Pointer Processor Scalable with 45 Gbit/s VT/STS & VC/AU3 Switch TXC-06965 DATA SHEET PRODUCT PREVIEW TXC-06965-MB, Ed. 2 March 2006 FEATURES APPLICATIONS • SDH/SONET line interface
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PHAST-48V
STM-16/OC-48
TXC-06965
TXC-06965-MB,
STM-16/STS-48
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PDF
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G706
Abstract: truth table varification
Text: XRT86SH328 PRELIMINARY SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND ARCHITECTURE DESC SEPTEMBER 2007 REV. P1.0.1 GENERAL DESCRIPTION The XRT86SH328 Voyager is a physical layer SONET/SDH to PDH mapper/demapper which enables T1/E1 aggregation to STS-3/STM-1 or STS1/
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XRT86SH328
28-T1/21-E1
VC-11/VC-12
G706
truth table varification
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NT1127
Abstract: E14112 E511 0x05D3 book national semiconductor GR-1230
Text: PHAST-48V Device STM-16/OC-48 SDH/SONET Overhead Terminator and Virtual Tributary Pointer Processor Scalable with 45 Gbit/s VT/STS & VC/AU3 Switch TXC-06965 DATA SHEET PRELIMINARY TXC-06965-MB, Ed. 3 March 2007 FEATURES APPLICATIONS • SDH/SONET line interface
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PHAST-48V
STM-16/OC-48
TXC-06965
TXC-06965-MB,
STM-16/STS-48
STM-16/STS-48
NT1127
E14112
E511
0x05D3
book national semiconductor
GR-1230
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PDF
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XRT75VL00
Abstract: GR-253 GR-253-CORE GR-499-CORE XRT75L03 XRT75VL00D ANSI T1.105.03B 1997 chn 347 CHN 932
Text: XRT75VL00D E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET SEPTEMBER 2008 REV. 1.0.4 • On-chip clock synthesizer provides the appropriate GENERAL DESCRIPTION rate clock from a single 12.288 MHz Clock. The XRT75VL00D is a single-channel fully integrated Line Interface Unit LIU with Sonet Desynchronizer
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XRT75VL00D
XRT75VL00D
XRT75VL00
GR-253
GR-253-CORE
GR-499-CORE
XRT75L03
ANSI T1.105.03B 1997
chn 347
CHN 932
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traffic light using 68K
Abstract: MCP860 AU-AIS alarm
Text: XRT86SH328 PRELIMINARY SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND ARCHITECTURE DESC SEPTEMBER 2007 REV. P1.0.0 GENERAL DESCRIPTION The XRT86SH328 Voyager is a physical layer SONET/SDH to PDH mapper/demapper which enables T1/E1 aggregation to STS-3/STM-1 or STS1/
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Original
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XRT86SH328
28-T1/21-E1
VC-11/VC-12
traffic light using 68K
MCP860
AU-AIS alarm
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PDF
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