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    SN74LV00A Search Results

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    SN74LV00APWR Texas Instruments Quadruple 2-Input Positive-NAND Gates 14-TSSOP -40 to 125 Visit Texas Instruments Buy
    SN74LV00ADR Texas Instruments Quadruple 2-Input Positive-NAND Gates 14-SOIC -40 to 125 Visit Texas Instruments Buy
    SN74LV00ARGYR Texas Instruments Quadruple 2-Input Positive-NAND Gates 14-VQFN -40 to 125 Visit Texas Instruments Buy
    SN74LV00ADGVR Texas Instruments Quadruple 2-Input Positive-NAND Gates 14-TVSOP -40 to 125 Visit Texas Instruments Buy
    SN74LV00ADBR Texas Instruments Quadruple 2-Input Positive-NAND Gates 14-SSOP -40 to 125 Visit Texas Instruments Buy
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    SN74LV00A Price and Stock

    Texas Instruments SN74LV00APWR

    IC GATE NAND 4CH 2-INP 14TSSOP
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    DigiKey SN74LV00APWR Cut Tape 7,243 1
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    SN74LV00APWR 1,188
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    SN74LV00APWR 848
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    Win Source Electronics SN74LV00APWR 79,650
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    Texas Instruments SN74LV00AD

    IC GATE NAND 4CH 2-INP 14SOIC
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    DigiKey SN74LV00AD Tube 4,225 1
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    Texas Instruments SN74LV00ANSR

    IC GATE NAND 4CH 2-INP 14SO
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    DigiKey SN74LV00ANSR Digi-Reel 4,000 1
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    Texas Instruments SN74LV00ARGYR

    IC GATE NAND 4CH 2-INP 14VQFN
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    DigiKey SN74LV00ARGYR Digi-Reel 2,880 1
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    Texas Instruments SN74LV00ADR

    IC GATE NAND 4CH 2-INP 14SOIC
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    DigiKey SN74LV00ADR Reel 2,500 2,500
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    SN74LV00ADR 3,288
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    SN74LV00ADR 1,077
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    SN74LV00ADR 640
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    Win Source Electronics SN74LV00ADR 9,236
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    SN74LV00A Datasheets (101)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    SN74LV00A Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND GATES Original PDF
    SN74LV00A Texas Instruments Quadruple 2-Input Positive-NAND Gates Original PDF
    SN74LV00AD Texas Instruments Logic - Gates and Inverters, Integrated Circuits (ICs), IC GATE NAND 4CH 2-INP 14-SOIC Original PDF
    SN74LV00AD Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND GATES Original PDF
    SN74LV00AD Texas Instruments Quadruple 2-Input Positive-NAND Gates 14-SOIC -40 to 85 Original PDF
    SN74LV00AD Texas Instruments SN74LV00 - Quadruple 2-Input Positive-NAND Gates 14-SOIC -40 to 85 Original PDF
    SN74LV00ADB Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND GATES Original PDF
    SN74LV00ADBLE Texas Instruments Quadruple 2-Input Positive-NAND Gates 14-SSOP -40 to 85 Original PDF
    SN74LV00ADBLE Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND GATES Original PDF
    SN74LV00ADBLE Texas Instruments SN74LV00 - Quadruple 2-Input Positive-NAND Gates 14-SSOP -40 to 85 Original PDF
    SN74LV00ADBR Texas Instruments Logic - Gates and Inverters, Integrated Circuits (ICs), IC GATE NAND 4CH 2-INP 14-SSOP Original PDF
    SN74LV00ADBR Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND GATES Original PDF
    SN74LV00ADBR Texas Instruments Quadruple 2-Input Positive-NAND Gates Original PDF
    SN74LV00ADBR Texas Instruments Quadruple 2-Input Positive-NAND Gates 14-SSOP -40 to 85 Original PDF
    SN74LV00ADBR Texas Instruments SN74LV00 - Quadruple 2-Input Positive-NAND Gates 14-SSOP -40 to 85 Original PDF
    SN74LV00ADBRG4 Texas Instruments Logic - Gates and Inverters, Integrated Circuits (ICs), IC GATE NAND 4CH 2-INP 14-SSOP Original PDF
    SN74LV00ADBRG4 Texas Instruments Quadruple 2-Input Positive-NAND Gates 14-SSOP -40 to 85 Original PDF
    SN74LV00ADBRG4 Texas Instruments SN74LV00 - Quadruple 2-Input Positive-NAND Gates 14-SSOP -40 to 85 Original PDF
    SN74LV00ADE4 Texas Instruments Logic - Gates and Inverters, Integrated Circuits (ICs), IC GATE NAND 4CH 2-INP 14-SOIC Original PDF
    SN74LV00ADE4 Texas Instruments Quadruple 2-Input Positive-NAND Gates 14-SOIC -40 to 85 Original PDF

    SN74LV00A Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    A115-A

    Abstract: C101 SN54LV00A SN74LV00A
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389G – SEPTEMBER 1997 – REVISED OCTOBER 2002 SN54LV00A . . . J OR W PACKAGE SN74LV00A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B


    Original     		PDF SN54LV00A, SN74LV00A SCLS389G SN54LV00A A115-A C101 SN54LV00A SN74LV00A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV00A, SN74LV00A SCLS389J 000-V A114-A) A115-A) SN54LV00A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389G – SEPTEMBER 1997 – REVISED OCTOBER 2002 SN54LV00A . . . J OR W PACKAGE SN74LV00A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B


    Original     		PDF SN54LV00A, SN74LV00A SCLS389G SN54LV00A SN74LV00A 000-V A114-A) A115-A)

    SN54LV00A

    Abstract: SN74LV00A
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389C – SEPTEMBER 1997 – REVISED MAY 2000 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV00A, SN74LV00A SCLS389C MIL-STD-883, SN54LV00A SN74LV00A

    LV00A

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389E – SEPTEMBER 1997 – REVISED AUGUST 2002 SN54LV00A . . . J OR W PACKAGE SN74LV00A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y


    Original     		PDF SN54LV00A, SN74LV00A SCLS389E SN54LV00A SN74LV00A 000-V A114-A) A115-A) LV00A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV00A, SN74LV00A SCLS389J 000-V A114-A) A115-A) SN54LV00A

    A115-A

    Abstract: C101 SN54LV00A SN74LV00A
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV00A, SN74LV00A SCLS389J A115-A C101 SN54LV00A SN74LV00A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV00A, SN74LV00A SCLS389J 000-V A114-A) A115-A) SN54LV00A SN74LV00A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV00A, SN74LV00A SCLS389J 000-V A114-A) A115-A) SN54LV00A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D Ioff Supports Partial-Power-Down Mode D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV00A . . . J OR W PACKAGE


    Original     		PDF SN54LV00A, SN74LV00A SCLS389J SN54LV00A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV00A, SN74LV00A SCLS389J 000-V A114-A) A115-A) SN54LV00A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV00A, SN74LV00A SCLS389J 000-V A114-A) A115-A) SN54LV00A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389G – SEPTEMBER 1997 – REVISED OCTOBER 2002 SN54LV00A . . . J OR W PACKAGE SN74LV00A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B


    Original     		PDF SN54LV00A, SN74LV00A SCLS389G SN54LV00A SN74LV00A 000-V A114-A) A115-A)

    A115-A

    Abstract: C101 SN54LV00A SN74LV00A
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV00A, SN74LV00A SCLS389J A115-A C101 SN54LV00A SN74LV00A

    lv00a

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV00A, SN74LV00A SCLS389J 000-V A114-A) A115-A) SN54LV00A lv00a

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV00A, SN74LV00A SCLS389J 000-V A114-A) A115-A) SN54LV00A

    A115-A

    Abstract: C101 SN54LV00A SN74LV00A
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV00A, SN74LV00A SCLS389J A115-A C101 SN54LV00A SN74LV00A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV00A, SN74LV00A SCLS389J 000-V A114-A) A115-A) SN54LV00A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV00A, SN74LV00A SCLS389J 000-V A114-A) A115-A) SN54LV00A

    LV00A

    Abstract: A115-A C101 SN54LV00A SN74LV00A 74lv00a
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389D – SEPTEMBER 1997 – REVISED JANUARY 2001 D D D D 2-V to 5.5-V VCC Operation Typical VOLP Output Ground Bounce <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN54LV00A, SN74LV00A SCLS389D 000-V A114-A) A115-A) SN54LV00A LV00A A115-A C101 SN54LV00A SN74LV00A 74lv00a

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV00A, SN74LV00A SCLS389J

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV00A, SN74LV00A SCLS389J 000-V A114-A) A115-A) SN54LV00A

    A115-A

    Abstract: C101 SN54LV00A SN74LV00A lv00a
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


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    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389B - SEPTEMBER 1997 - REVISED APRIL 1998 EPIC Enhanced-Performance implanted CMOS Process SN54LVOOA . . J OR W PACKAGE SN74LV00A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) Typical V q l p (Output Ground Bounce)


    OCR Scan     		PDF SN54LV00A, SN74LV00A SCLS389B JESD17 MIL-STD-883, 300-mil SN54LVOOA SN74LV00A