ls125a
Abstract: ls126A 74LS126A 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Text: SN54/74LS125A SN54/74LS126A QUAD 3-STATE BUFFERS VCC E D O E D O 14 13 12 11 10 9 8 QUAD 3-STATE BUFFERS LOW POWER SCHOTTKY 1 2 3 E D O 4 5 6 7 E D O GND LS125A J SUFFIX CERAMIC CASE 632-08 VCC E D O E D O 14 13 12 11 10 9 8 14 1 N SUFFIX PLASTIC CASE 646-06
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SN54/74LS125A
SN54/74LS126A
LS125A
LS126A
51A-02
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
ls125a
ls126A
74LS126A
751A-02
SN54LSXXXJ
SN74LSXXXD
SN74LSXXXN
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74LS386
Abstract: SN54/74LS386 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74LS386DC
Text: SN54/74LS386 QUAD 2-INPUT EXCLUSIVE-OR GATE QUAD 2-INPUT EXCLUSIVE-OR GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 14 1 1 2 3 4 5 6 7 GND N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION
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SN54/74LS386
51A-02
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
74LS386
SN54/74LS386
751A-02
SN54LSXXXJ
SN74LSXXXD
SN74LSXXXN
74LS386DC
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74LS390
Abstract: 74LS393 equivalent 74LS393 LS290 LS293 LS390 LS393
Text: SN54/74LS390 SN54/74LS393 DUAL DECADE COUNTER; DUAL 4-STAGE BINARY COUNTER The SN54 / 74LS390 and SN54 / 74LS393 each contain a pair of high-speed 4-stage ripple counters. Each half of the LS390 is partitioned into a divide-by-two section and a divide-by five section, with a separate clock input
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SN54/74LS390
SN54/74LS393
74LS390
74LS393
LS390
LS393
Modulo-16
LS393,
74LS393 equivalent
LS290
LS293
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74ls166
Abstract: 74ls gate symbols 74LS TTL 74ls166 datasheet 74LS LS166 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Text: SN54/74LS166 8-BIT SHIFT REGISTERS The SN54L/ 74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 54/ 74LS standard load. By utilizing input clamping diodes, switching transients are minimized and
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SN54/74LS166
SN54L/
74LS166
LS166
74ls gate symbols
74LS TTL
74ls166 datasheet
74LS
SN54LSXXXJ
SN74LSXXXD
SN74LSXXXN
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LS645
Abstract: 74ls642 SN54/74LS642 SN54LSXXXJ LS640 LS641 LS642 74LS645 8A79 74LS641
Text: SN54/74LS640 SN54/74LS641 SN54/74LS642 SN54/74LS645 OCTAL BUS TRANSCEIVERS These octal bus transceivers are designed for asynchronous two-way communication between data buses. Control function implementation minimizes external timing requirements. These circuits allow data transmission from the A bus to B or from the B bus to A bus depending upon the logic
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SN54/74LS640
SN54/74LS641
SN54/74LS642
SN54/74LS645
LS640
LS641
LS642
LS645
LS645
74ls642
SN54/74LS642
SN54LSXXXJ
LS640
LS641
LS642
74LS645
8A79
74LS641
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74LS147
Abstract: 74ls147 pin diagram FUNCTIONAL APPLICATION OF 74LS148 74ls148 74LS147 equivalent motorola 74ls147 74ls748 SN54/74LS147 FAST AND LS TTL ls74
Text: SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54/ 74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are
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SN54/74LS147
SN54/74LS148
SN54/74LS748
10-LINE-TO-4-LINE
74LS147
74LS148
LS147
LS148
74ls147 pin diagram
FUNCTIONAL APPLICATION OF 74LS148
74LS147 equivalent
motorola 74ls147
74ls748
SN54/74LS147
FAST AND LS TTL
ls74
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74LS245 application
Abstract: logic diagram of 74LS245 74ls245 74ls245 motorola TTL 5400 motorola SN54/74LS245 751d-03 SN54LSXXXJ SN74LSXXXN motorola TTL 5400
Text: SN54/74LS245 OCTAL BUS TRANSCEIVER The SN54 / 74LS245 is an Octal Bus Transmitter/Receiver designed for 8-line asynchronous 2-way data communication between data buses. Direction Input DR controls transmission of Data from bus A to bus B or bus B to bus A depending upon its logic level. The Enable input (E) can be used
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SN54/74LS245
74LS245
74LS245 application
logic diagram of 74LS245
74ls245 motorola
TTL 5400 motorola
SN54/74LS245
751d-03
SN54LSXXXJ
SN74LSXXXN
motorola TTL 5400
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TOP 242 PN
Abstract: TTL 74145 LS 74145 74LS145 SN74LSXXXD SN74LSXXXN SN54LSXXXJ 751B-03
Text: SN54/74LS145 1-OF-10 DECODER/DRIVER OPEN-COLLECTOR The SN54 / 74LS145, 1-of-10 Decoder/Driver, is designed to accept BCD inputs and provide appropriate outputs to drive 10-digit incandescent displays. All outputs remain off for all invalid binary input conditions. It is
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SN54/74LS145
1-OF-10
74LS145,
10-digit
TOP 242 PN
TTL 74145
LS 74145
74LS145
SN74LSXXXD
SN74LSXXXN
SN54LSXXXJ
751B-03
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74ls290
Abstract: LS290 74LS293 751A-02 LS293 LS90 LS93 74LS293 Asynchronous counter
Text: SN54/74LS290 SN54/74LS293 DECADE COUNTER; 4-BIT BINARY COUNTER The SN54 / 74LS290 and SN54/ 74LS293 are high-speed 4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two section and either a divide-by-five LS290 or divide-by-eight (LS293) section
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SN54/74LS290
SN54/74LS293
74LS290
74LS293
LS290)
LS293)
Modulo-16
LS290
42uthorized
751A-02
LS293
LS90
LS93
74LS293 Asynchronous counter
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74LS299 APPLICATION NOTE
Abstract: 74LS299 74LS299 APPLICATIONS SN54LSXXXJ SN74LSXXXN
Text: SN54/74LS299 8-BIT SHIFT/STORAGE REGISTER WITH 3-STATE OUTPUTS The SN54 / 74LS299 is an 8-Bit Universal Shift / Storage Register with 3-state outputs. Four modes of operation are possible: hold store , shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the
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SN54/74LS299
74LS299
74LS299 APPLICATION NOTE
74LS299 APPLICATIONS
SN54LSXXXJ
SN74LSXXXN
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motorola zc 5276
Abstract: 74LS158 circuit diagram of 32-1 multiplexer LS158 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Text: SN54/74LS158 QUAD 2-INPUT MULTIPLEXER The LSTTL/ MSI SN54L/ 74LS158 is a high speed Quad 2-input Multiplexer. It selects four bits of data from two sources using the common Select and Enable inputs. The four buffered outputs present the selected data in the
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SN54/74LS158
SN54L/
74LS158
LS158
motorola zc 5276
circuit diagram of 32-1 multiplexer
SN54LSXXXJ
SN74LSXXXD
SN74LSXXXN
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74LS112A
Abstract: 74LS112 SN54/74LS112A truth table NOT gate 74 SN54LSXXXJ SN74LSXXXD SN74LSXXXN JD16
Text: SN54/74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the
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SN54/74LS112A
74LS112A
74LS112
SN54/74LS112A
truth table NOT gate 74
SN54LSXXXJ
SN74LSXXXD
SN74LSXXXN
JD16
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motorola 74LS670
Abstract: Dip 28 motorola 74LS170 74LS670 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Text: SN54/74LS670 4 x 4 REGISTER FILE WITH 3-STATE OUTPUTS The TTL / MSI SN54 / 74LS670 is a high-speed, low-power 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address and enable, allow simultaneous read and write operation.
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SN54/74LS670
74LS670
74LS170
motorola 74LS670
Dip 28 motorola
SN54LSXXXJ
SN74LSXXXD
SN74LSXXXN
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74LS259
Abstract: demultiplexer truth table SN54/74LS259 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Text: SN54/74LS259 8-BIT ADDRESSABLE LATCH The SN54/ 74LS259 is a high-speed 8-Bit Addressable Latch designed for general purpose storage applications in digital systems. It is a multifunctional device capable of storing single line data in eight addressable latches, and
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SN54/74LS259
74LS259
demultiplexer truth table
SN54/74LS259
SN54LSXXXJ
SN74LSXXXD
SN74LSXXXN
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74LS348
Abstract: G104 74LS848 LS348 SN54LSXXXJ SN74LSXXXN
Text: SN54/74LS348 SN54/74LS848 8-INPUT PRIORITY ENCODERS WITH 3-STATE OUTPUTS The SN54 / 74LS348 and the SN54 / 74LS848 are eight input priority encoders which provide the 8-line to 3-line function. The outputs A0 – A2 and inputs (0 – 7) are active low. The active low input
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SN54/74LS348
SN54/74LS848
74LS348
74LS848
G104
LS348
SN54LSXXXJ
SN74LSXXXN
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ls378
Abstract: 74LS377 74LS174 74LS175 74LS378 74LS379
Text: SN54/74LS377 SN54/74LS378 SN54/74LS379 OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 / 74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a
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SN54/74LS377
SN54/74LS378
SN54/74LS379
74LS377
74LS378
74LS174,
74LS379
74LS175
74LS379
ls378
74LS174
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Untitled
Abstract: No abstract text available
Text: SN54/74LS640 SN54/74LS641 SN54/74LS642 SN54/74LS645 OCTAL BUS TRANSCEIVERS These octal bus transceivers are designed for asynchronous two-way communication between data buses. Control function implementation minimizes external timing requirements. These circuits allow data transmission from the A bus to B or from the B bus to A bus depending upon the logic
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SN54/74LS640
SN54/74LS641
SN54/74LS642
SN54/74LS645
LS640
LS641
LS642
LS645
732torola
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74LS192 truth table
Abstract: 74LS193 truth table 74LS192 PIN diagram 74ls193 74LS192 74LS192 INTERNAL DIAGRAM TTL 74ls193 74LS193 pin data 74LS192 table ttl 74ls192
Text: SN54/74LS192 SN54/74LS193 PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER PRESETTABLE BCD/ DECADE UP/ DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/ DOWN COUNTER The SN54/74LS192 is an UP/DOWN BCD Decade 8421 Counter and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate
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SN54/74LS192
SN54/74LS193
SN54/74LS192
SN54/74LS193
MODULO-16
74LS192 truth table
74LS193 truth table
74LS192 PIN diagram
74ls193
74LS192
74LS192 INTERNAL DIAGRAM
TTL 74ls193
74LS193 pin data
74LS192 table
ttl 74ls192
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74LS273
Abstract: pin diagram of 74ls273 1619CP SN54LSXXXJ SN74LSXXXN
Text: SN54/74LS273 OCTAL D FLIP-FLOP WITH CLEAR The SN54 / 74LS273 is a high-speed 8-Bit Register. The register consists of eight D-Type Flip-Flops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3
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SN54/74LS273
74LS273
20-pin
pin diagram of 74ls273
1619CP
SN54LSXXXJ
SN74LSXXXN
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74LS194A
Abstract: LS195A SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Text: SN54/74LS194A 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER The SN54 / 74LS194A is a High Speed 4-Bit Bidirectional Universal Shift Register. As a high speed multifunctional sequential building block, it is useful in a wide variety of applications. It may be used in serial-serial, shift left, shift
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SN54/74LS194A
74LS194A
LS194A
LS195A
SN54LSXXXJ
SN74LSXXXD
SN74LSXXXN
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TTL 74ls133
Abstract: 74ls133 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Text: SN54/74LS133 13-INPUT NAND GATE 13-INPUT NAND GATE VCC 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 GND LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN
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SN54/74LS133
13-INPUT
751B-03
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
TTL 74ls133
74ls133
SN54LSXXXJ
SN74LSXXXD
SN74LSXXXN
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SN54LSXXXJ
Abstract: No abstract text available
Text: <8> MOTOROLA SN54/74LS260 DUAL 5-INPUT NOR GATE DUAL 5-INPUT NOR GATE vcc LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 632-08 GND 1 N SUFFIX FrP csss, 1 D SUFFIX SOIC CASE 751A-02 5 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES
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SN54/74LS260
51A-02
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
SN54/74LS260
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Untitled
Abstract: No abstract text available
Text: g MOTOROLA SN74LS136 QUAD 2-INPUT EXCLUSIVE OR GATE QUAD 2-INPUT EXCLUSIVE OR GATE LOW PO W ER SCH O TTKY vcc fui [ïïi [ïïi nn nói m rn J SUFFIX C E R A M IC C A S E 632-08 14 L_J LAJ LU LAJ LU LU L I 1 GND •OPEN COLLECTOR OUTPUTS N SUFFIX PLA STIC
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SN74LS136
51A-02
54LSXXXJ
SN74LSXXXD
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Untitled
Abstract: No abstract text available
Text: MOTOROLA SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The S N 54/74LS 114A offers common clock and common d e a r inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be
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SN54/74LS114A
54/74LS
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