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    SN54LV132A Search Results

    SN54LV132A Datasheets (7)

    Part ECAD Model Manufacturer Description Curated Type PDF
    SN54LV132A Texas Instruments QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS Original PDF
    SN54LV132AFK Texas Instruments QUADRUPLE POSITIVE-NAND GATE WITH SCHMITT-TRIGGER INPUTS Original PDF
    SN54LV132AFK Texas Instruments QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS Original PDF
    SN54LV132AJ Texas Instruments QUADRUPLE POSITIVE-NAND GATE WITH SCHMITT-TRIGGER INPUTS Original PDF
    SN54LV132AJ Texas Instruments QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS Original PDF
    SN54LV132AW Texas Instruments QUADRUPLE POSITIVE-NAND GATE WITH SCHMITT-TRIGGER INPUTS Original PDF
    SN54LV132AW Texas Instruments QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS Original PDF

    SN54LV132A Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    SN74LV132APWR

    Abstract: A115-A C101 LV132A SN54LV132A SN74LV132A
    Text: SN54LV132A, SN74LV132A QUADRUPLE POSITIVEĆNAND GATES WITH SCHMITTĆTRIGGER INPUTS SCLS394H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9 ns at 5 V D Typical VOLP Output Ground Bounce D D D <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN54LV132A, SN74LV132A SCLS394H 000-V A114-A) A115-A) SN54LV132A SN74LV132APWR A115-A C101 LV132A SN54LV132A SN74LV132A

    LV132A

    Abstract: SN54LV132A SN74LV132A
    Text: SN54LV132A, SN74LV132A QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS394B – APRIL 1998 – REVISED AUGUST 1998 D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C


    Original     		PDF SN54LV132A, SN74LV132A SCLS394B MIL-STD-883, SN54LV132A LV132A SN54LV132A SN74LV132A

    A115-A

    Abstract: C101 LV132A SN54LV132A SN74LV132A
    Text: SN54LV132A, SN74LV132A QUADRUPLE POSITIVEĆNAND GATES WITH SCHMITTĆTRIGGER INPUTS SCLS394H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9 ns at 5 V D Typical VOLP Output Ground Bounce D D D <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN54LV132A, SN74LV132A SCLS394H 000-V A114-A) A115-A) SN54LV132A A115-A C101 LV132A SN54LV132A SN74LV132A

    A115-A

    Abstract: C101 LV132A SN54LV132A SN74LV132A
    Text: SN54LV132A, SN74LV132A www.ti.com SCLS394I – APRIL 1999 – REVISED JUNE 2010 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS Check for Samples: SN54LV132A, SN74LV132A FEATURES 1 • • • • 2-V to 5.5-V VCC Operation Max tpd of 9 ns at 5 V


    Original     		PDF SN54LV132A, SN74LV132A SCLS394I 000-V A114-A) A115-A) SN54LV132A. A115-A C101 LV132A SN54LV132A SN74LV132A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV132A, SN74LV132A QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS394C – APRIL 1998 – REVISED MAY 2000 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN54LV132A, SN74LV132A SCLS394C MIL-STD-883, SN74LV132A, ////roarer/root/data13/imaging/BIT. /08032000/TXII/08022000/sn74lv132a SDYU001M, SCAU001A, SCEM128,

    Untitled

    Abstract: No abstract text available
    Text: SN54LV132A, SN74LV132A QUADRUPLE POSITIVEĆNAND GATES WITH SCHMITTĆTRIGGER INPUTS SCLS394H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9 ns at 5 V D Typical VOLP Output Ground Bounce D D D <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN54LV132A, SN74LV132A SCLS394H 000-V A114-A) A115-A) SN54LV132A

    A115-A

    Abstract: C101 LV132A SN54LV132A SN74LV132A
    Text: SN54LV132A, SN74LV132A QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS394D – APRIL 1998 – REVISED JANUARY 2001 D D D D SN54LV132A . . . J OR W PACKAGE SN74LV132A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)


    Original     		PDF SN54LV132A, SN74LV132A SCLS394D SN54LV132A 000-V A114-A) A115-A) A115-A C101 LV132A SN54LV132A SN74LV132A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV132A, SN74LV132A QUADRUPLE POSITIVEĆNAND GATES WITH SCHMITTĆTRIGGER INPUTS SCLS394H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9 ns at 5 V D Typical VOLP Output Ground Bounce D D D <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN54LV132A, SN74LV132A SCLS394H SN54LV132A SN74LV132A LV132A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV132A, SN74LV132A QUADRUPLE POSITIVEĆNAND GATES WITH SCHMITTĆTRIGGER INPUTS SCLS394H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9 ns at 5 V D Typical VOLP Output Ground Bounce D D D <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN54LV132A, SN74LV132A SCLS394H SN54LV132A SN74LV132A LV132A

    LV132A

    Abstract: A115-A C101 SN54LV132A SN74LV132A
    Text: SN54LV132A, SN74LV132A QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS394D – APRIL 1998 – REVISED JANUARY 2001 D D D D SN54LV132A . . . J OR W PACKAGE SN74LV132A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)


    Original     		PDF SN54LV132A, SN74LV132A SCLS394D SN54LV132A 000-V A114-A) A115-A) LV132A A115-A C101 SN54LV132A SN74LV132A

    A115-A

    Abstract: C101 LV132A SN54LV132A SN74LV132A
    Text: SN54LV132A, SN74LV132A QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS394D – APRIL 1998 – REVISED JANUARY 2001 D D D D SN54LV132A . . . J OR W PACKAGE SN74LV132A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)


    Original     		PDF SN54LV132A, SN74LV132A SCLS394D SN54LV132A 000-V A114-A) A115-A) A115-A C101 LV132A SN54LV132A SN74LV132A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV132A, SN74LV132A QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS394D – APRIL 1998 – REVISED JANUARY 2001 D D D D SN54LV132A . . . J OR W PACKAGE SN74LV132A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)


    Original     		PDF SN54LV132A, SN74LV132A SCLS394D 000-V A114-A) A115-A) SN54LV132A SN74LV132A

    A115-A

    Abstract: C101 LV132A SN54LV132A SN74LV132A
    Text: SN54LV132A, SN74LV132A QUADRUPLE POSITIVEĆNAND GATES WITH SCHMITTĆTRIGGER INPUTS SCLS394H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9 ns at 5 V D Typical VOLP Output Ground Bounce D D D <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN54LV132A, SN74LV132A SCLS394H 000-V A114-A) A115-A) SN54LV132A A115-A C101 LV132A SN54LV132A SN74LV132A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV132A, SN74LV132A www.ti.com SCLS394I – APRIL 1999 – REVISED JUNE 2010 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS Check for Samples: SN54LV132A, SN74LV132A FEATURES 1 • • • • 2-V to 5.5-V VCC Operation Max tpd of 9 ns at 5 V


    Original     		PDF SN54LV132A, SN74LV132A SCLS394I 000-V A114-A) A115-A) SN54LV132A.

    Untitled

    Abstract: No abstract text available
    Text: SN54LV132A, SN74LV132A QUADRUPLE POSITIVEĆNAND GATES WITH SCHMITTĆTRIGGER INPUTS SCLS394H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9 ns at 5 V D Typical VOLP Output Ground Bounce D D D <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN54LV132A, SN74LV132A SCLS394H SN54LV132A SN74LV132A LV132A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV132A, SN74LV132A QUADRUPLE POSITIVEĆNAND GATES WITH SCHMITTĆTRIGGER INPUTS SCLS394H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9 ns at 5 V D Typical VOLP Output Ground Bounce D D D <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN54LV132A, SN74LV132A SCLS394H SN54LV132A SN74LV132A LV132A

    LV132A

    Abstract: A115-A C101 SN54LV132A SN74LV132A
    Text: SN54LV132A, SN74LV132A QUADRUPLE POSITIVEĆNAND GATES WITH SCHMITTĆTRIGGER INPUTS SCLS394G − APRIL 1998 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 9 ns at 5 V D Typical VOLP Output Ground Bounce D D D <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN54LV132A, SN74LV132A SCLS394G 000-V A114-A) A115-A) SN54LV132A LV132A A115-A C101 SN54LV132A SN74LV132A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV132A, SN74LV132A QUADRUPLE POSITIVEĆNAND GATES WITH SCHMITTĆTRIGGER INPUTS SCLS394H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9 ns at 5 V D Typical VOLP Output Ground Bounce D D D <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN54LV132A, SN74LV132A SCLS394H SN54LV132A SN74LV132A LV132A

    LV132A

    Abstract: SN54LV132A SN74LV132A SN74LV132AD SN74LV132ADBR SN74LV132ADR SN74LV132ANSR SN74LV132APW SN74LV132APWR SN74LV132APWT
    Text: SN54LV132A, SN74LV132A QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS394E – APRIL 1998 – REVISED JULY 2003 D D D D SN54LV132A . . . J OR W PACKAGE SN74LV132A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Max tpd of 9 ns at 5 V


    Original     		PDF SN54LV132A, SN74LV132A SCLS394E SN54LV132A 000-V A114-A) A115-A) LV132A SN54LV132A SN74LV132A SN74LV132AD SN74LV132ADBR SN74LV132ADR SN74LV132ANSR SN74LV132APW SN74LV132APWR SN74LV132APWT

    Untitled

    Abstract: No abstract text available
    Text: SN54LV132A, SN74LV132A QUADRUPLE POSITIVEĆNAND GATES WITH SCHMITTĆTRIGGER INPUTS SCLS394H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9 ns at 5 V D Typical VOLP Output Ground Bounce D D D <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN54LV132A, SN74LV132A SCLS394H SN54LV132A SN74LV132A LV132A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV132A, SN74LV132A www.ti.com SCLS394I – APRIL 1999 – REVISED JUNE 2010 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS Check for Samples: SN54LV132A, SN74LV132A FEATURES 1 • • • • 2-V to 5.5-V VCC Operation Max tpd of 9 ns at 5 V


    Original     		PDF SN54LV132A, SN74LV132A SCLS394I 000-V A114-A) A115-A) SN54LV132A.

    Untitled

    Abstract: No abstract text available
    Text: SN54LV132A, SN74LV132A www.ti.com SCLS394I – APRIL 1999 – REVISED JUNE 2010 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS Check for Samples: SN54LV132A, SN74LV132A FEATURES 1 • • • • 2-V to 5.5-V VCC Operation Max tpd of 9 ns at 5 V


    Original     		PDF SN54LV132A, SN74LV132A SCLS394I 000-V A114-A) A115-A) SN54LV132A.

    LV132A

    Abstract: No abstract text available
    Text: SN54LV132A, SN74LV132A www.ti.com SCLS394I – APRIL 1999 – REVISED JUNE 2010 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS Check for Samples: SN54LV132A, SN74LV132A FEATURES 1 • • • • 2-V to 5.5-V VCC Operation Max tpd of 9 ns at 5 V


    Original     		PDF SN54LV132A, SN74LV132A SCLS394I 000-V A114-A) A115-A) SN54LV132A. LV132A

    39-4B

    Abstract: No abstract text available
    Text: SN54LV132A, SN74LV132A QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS S C LS 394B - A P R IL 1998 - R EVISED A U G U S T 1998 EPIC Enhanced-Performance Implanted CMOS Process SN54LV132A . . . J OR W PACKAGE SN74LV132A . . . D, DB, DGV, NS, OR PW PACKAGE


    OCR Scan     		PDF SN54LV132A, SN74LV132A MIL-STD-883, SN54LV132A SN74LV1m 39-4B