22C23
Abstract: gic 1990 TMS87C257
Text: TMS87C257 262 144-BIT LATCHED UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY SMLS857 — N O VEM BER 1990 • Organization . . . 32K x 8 • Single 5-V Power Supply • Intergrated Address Latch J Package Top View A S /V p p [ • Max Access/Min Cycle Time (Vcc ± 5%)
|
OCR Scan
|
PDF
|
TMS87C257
144-BIT
SMLS857
TMS87C257-150
TMS87C257-1
TMS87C257-2
A0-A14
22C23
gic 1990
|
TMS87*257
Abstract: No abstract text available
Text: TMS87C257 262 144-BIT LATCHED UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY SMLS857 — NOVEMBER 1990 Organization . . . 32K x 8 J Package Top View Single 5-V Power Supply A S /V p p [ 1 Intergrated Address Latch Max Access/Mln Cycle Time (Vcc ± 5%) TMS87C257-150 150 ns
|
OCR Scan
|
PDF
|
TMS87C257
144-BIT
SMLS857
TMS87C257-150
TMS87C257-1
TMS87C257-2
144-bit,
AO-A14
TMS87*257
|
C 5121-00
Abstract: s48c tlc 1125 2811DZ D7528 TL500 TL 413 tl501 tlc1125 TLC7533
Text: SYSTEM/SERVO CIRCUITS SELECTION GUIDE data acquisition and conversion single-slope and dual-slope converters values specified for Ta = 25 C DESCRIPTION RESOLUTION SPEED (ms) 4 1/2 Digits 34 Dual-slope A/D with BCD output Dual-slope analog processors TYPE
|
OCR Scan
|
PDF
|
SLYD002
SLYD002
TLC7135
ICL7135
TL500
TL501
TL502
TL503
C 5121-00
s48c
tlc 1125
2811DZ
D7528
TL 413
tl501
tlc1125
TLC7533
|
TMS87C257
Abstract: 87C257
Text: TMS87C257 262 144-BIT LATCHED UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY SM LS 857 — N O V E M B E R 1990 • Organization . . . 32K • Single 5-V Power Supply • Intergrated Address Latch • • • • • x 8 j Package Top View A S /V p p [ 1 A12[ 2
|
OCR Scan
|
PDF
|
TMS87C257
144-BIT
SMLS857
TMS87C257-150
TMS87C257-1
TMS87C257-2
A0-A14
87C257
|