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    LPDDR3 layout

    Abstract: No abstract text available
    Text: TI Information — Selective Disclosure TPS51116 www.ti.com SLUS609I – MAY 2004 – REVISED JANUARY 2014 Complete DDR, DDR2, DDR3, and LPDDR3 Memory Power Solution Synchronous Buck Controller, 3-A LDO, Buffered Reference Check for Samples: TPS51116 FEATURES


    Original     		TPS51116 SLUS609I TPS51116 DDR2/SSTL-18, DDR3/SSTL-15, 400-kHz, LPDDR3 layout PDF

    Untitled

    Abstract: No abstract text available
    Text: TI Information — Selective Disclosure TPS51116 www.ti.com SLUS609I – MAY 2004 – REVISED JANUARY 2014 Complete DDR, DDR2, DDR3, and LPDDR3 Memory Power Solution Synchronous Buck Controller, 3-A LDO, Buffered Reference Check for Samples: TPS51116 FEATURES


    Original     		TPS51116 SLUS609I TPS51116 DDR2/SSTL-18, DDR3/SSTL-15, 400-kHz, PDF