SLLZ041B Search Results

PCI2050A

Abstract: PCI2050B
Text: Errata SLLZ041B – January 2005 – Revised April 2009 PCI2050B Errata 1 Errata #1 1.1 Brief Description of Issue Trst – CLK timing is out of specification. 1.2 Detailed Description of Issue When PCI2050B is in 66-MHz primary, 33-MHz secondary mode, the dividing DFF is in reset when