m-bus
Abstract: bus arbitration protocol MC68681 PROGRAMMING EXAMPLE MC68681 MCF5307 sbx 1810
Text: INDEX A accumulator ACC , 3-11 addressing mode summary, 3-20 B BDM, 2-14 BDM/JTAG signals test clock (TCK), 2-14 test data input/development serial input (TDI/DSI), 2-14 test data output/development serial output (TDO/DSO), 2-15 test mode select/break point (TMS/BKPT),
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MC68681,
MCF5307
Index-11
Index-12
m-bus
bus arbitration protocol
MC68681 PROGRAMMING EXAMPLE
MC68681
sbx 1810
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Untitled
Abstract: No abstract text available
Text: BTSD08 SerDes Test Device Description Features The adoption of serial link technology in VPX and ATCA poses significant • Multi-lane differential serial fabric test unit debug, characterization, and test challenges. The BTSD08 is an ultra low cost • Flexible design allows signal analysis for various architectures
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BTSD08
BTSD08,
anBTSD08
BTSD08
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LF3312
Abstract: TDI timing
Text: JTAG Boundary Scan Testing LF3312 - Application Note IEEE 1149.1 Serial Boundary Scan JTAG The LF3312 incorporates a serial boundary scan test access port (TAP) in its BGA package. This device is compliant with IEEE Standard #1149.1-1900. Test Access Port Clock - TCK
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LF3312
TDI timing
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AN889
Abstract: 8 bit LFSR for test pattern generation AN-889 C1996 SCANPSC100F 32 Bit Counter parallel to serial conversion in C IEEE paper simple LFSR PSC100F AN-889 national
Text: National Semiconductor Application Note 889 Jay Brown April 1993 ABSTRACT The IEEE Std 1149 1 Standard Test Access Port and Boundary-Scan Architecture1 as well as other scan path methodologies use a serial interface for transmitting data to and from the circuit under test This serial communication
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SCANPSC100F
AN889
8 bit LFSR for test pattern generation
AN-889
C1996
32 Bit Counter
parallel to serial conversion in C IEEE paper
simple LFSR
PSC100F
AN-889 national
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MAX232 IC PIN DETAILS
Abstract: EDE700 max232 level shifter 16c84 40 pin LCD connector HD44780 MAX232 PIC16C621 PIC16C84 T2400
Text: EDE700 Serial LCD Interface IC EDE700 0=2400,1=9600 1 BAUD 0=Inverted,1=Standard 2 POLARITY 0=Diagnostic Mode 3 Connect to +5V DC XMIT 18 Serial Transmit RCV 17 Serial Receive TEST OSC1 16 Oscillator Connection 4 +5V OSC2 15 Oscillator Connection Digital Ground
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EDE700
EDE700
MAX232 IC PIN DETAILS
max232 level shifter
16c84
40 pin LCD connector
HD44780
MAX232
PIC16C621
PIC16C84
T2400
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Untitled
Abstract: No abstract text available
Text: SCANPSC100F Embedded Boundary Scan Controller IEEE 1149.1 Support General Description Features The SCANPSC100F is designed to interface a generic parallel processor bus to a serial scan test bus. It is useful in improving scan throughput when applying serial vectors to system test circuitry and reduces the software overhead that is
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SCANPSC100F
PSC100F
scaCANPSC100FMW
5962-9475001QYA
SCANSTA101WQML
2-Sep-2000]
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SCANPSC100FSC
Abstract: SCANPSC100FSCX SCANPSC100F SCANPSC100FFMQB
Text: SCANPSC100F Embedded Boundary Scan Controller IEEE 1149.1 Support General Description Features The SCANPSC100F is designed to interface a generic parallel processor bus to a serial scan test bus. It is useful in improving scan throughput when applying serial vectors to system test circuitry and reduces the software overhead that is
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SCANPSC100F
SCANPSC100F
PSC100F
SCANPSC100FSC
SCANPSC100FSCX
SCANPSC100FFMQB
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SCANPSC100F
Abstract: fairchild tdi 1999 Dynamic Memory Refresh Controller
Text: SCANPSC100F Embedded Boundary Scan Controller IEEE 1149.1 Support General Description Features The SCANPSC100F is designed to interface a generic parallel processor bus to a serial scan test bus. It is useful in improving scan throughput when applying serial vectors to system test circuitry and reduces the software overhead that is
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SCANPSC100F
SCANPSC100F
PSC100F
fairchild tdi 1999
Dynamic Memory Refresh Controller
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SCANPSC100F
Abstract: Dynamic Memory Refresh Controller
Text: SCANPSC100F Embedded Boundary Scan Controller IEEE 1149.1 Support General Description Features The SCANPSC100F is designed to interface a generic parallel processor bus to a serial scan test bus. It is useful in improving scan throughput when applying serial vectors to system test circuitry and reduces the software overhead that is
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SCANPSC100F
SCANPSC100F
PSC100F
indepe959
Dynamic Memory Refresh Controller
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SCANPSC110F
Abstract: SCANPSC110FDMQB SCANPSC110FFMQB SCANPSC110FLMQB SCANPSC110FSC SCANPSC110FSCX
Text: General Description Features The SCANPSC110F Bridge extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a hierarchical approach over a single serial scan chain is improved test throughput and the ability to remove a
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SCANPSC110F
32-bit
cou85
ds011570
SCANPSC110FDMQB
SCANPSC110FFMQB
SCANPSC110FLMQB
SCANPSC110FSC
SCANPSC110FSCX
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AN3964
Abstract: APP3964 MAX9218 MAX9247 MAX9248 MAX9250 PRBS
Text: Maxim > App Notes > AUTOMOTIVE CLOCK GENERATION AND DISTRIBUTION HIGH-SPEED SIGNAL PROCESSING Keywords: Test Mode, PRBS, MAX9247, LVDS Testing, Serializer HIGH-SPEED INTERCONNECT Dec 15, 2006 APPLICATION NOTE 3964 Enabling Test Modes on the MAX9247 Abstract: The MAX9247 features an internal test mode, which is useful for debugging the serial link or
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MAX9247,
MAX9247
MAX9247
27-bit,
42MHz
com/an3964
MAX9218:
AN3964
APP3964
MAX9218
MAX9248
MAX9250
PRBS
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APP3480
Abstract: No abstract text available
Text: Maxim > App Notes > MICROCONTROLLERS Keywords: MAXQ, JTAG, serial to JTAG, test access port, serial-to-jtag, TAP controller, microprocessor Mar 23, 2005 APPLICATION NOTE 3480 The Serial-to-JTAG Board for MAXQ Processors Abstract: This application note discusses the commands accepted by the Serial-to-JTAG board. This board is used
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com/an3480
AN3480,
APP3480,
Appnote3480,
APP3480
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SCANPSC110
Abstract: SCANPSC110F SCANPSC110FDMQB SCANPSC110FFMQB SCANPSC110FLMQB
Text: SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port IEEE1149.1 System Test Support General Description The SCANPSC110F Bridge extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a hierarchical approach over a single serial scan
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SCANPSC110F
IEEE1149
SCANPSC110F
SCANPSC110
SCANPSC110FDMQB
SCANPSC110FFMQB
SCANPSC110FLMQB
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SCANPSC110F
Abstract: SCANPSC110FDMQB SCANPSC110FFMQB SCANPSC110FLMQB
Text: SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port IEEE1149.1 System Test Support General Description Features The SCANPSC110F Bridge extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a hierarchical approach over a single serial scan
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SCANPSC110F
IEEE1149
SCANPSC110F
SCANPSC110FDMQB
SCANPSC110FFMQB
SCANPSC110FLMQB
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MAX1069
Abstract: MAX1169 MAX1169ACUD MAX1169AEUD MAX1169BCUD MAX1169BEUD MAX1169CCUD MAX1169CEUD
Text: 19-2654; Rev 0; 10/02 58.6ksps, 16-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP Applications Hand-Held Portable Applications Medical Instruments Battery-Powered Test Equipment Solar-Powered Remote Systems Features ♦ High-Speed Serial Interface 400kHz Fast Mode
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16-Bit,
14-Pin
400kHz
50ksps
10ksps
MAX1169ACUD*
MAX1169
MAX1069
MAX1169
MAX1169ACUD
MAX1169AEUD
MAX1169BCUD
MAX1169BEUD
MAX1169CCUD
MAX1169CEUD
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Untitled
Abstract: No abstract text available
Text: Model DLC08 Revere High-Performance Digital Load Cell Interface FEATURES • Serial interface RS-485 • All settings made through the serial interface • Simple calibration, test and setting via HyperTerminal programming, or via Revere’s software • Automatic unit conversion, zero tracking
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DLC08
RS-485)
27-Apr-2011
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lfsr16
Abstract: SCANPSC110FFMQB SCANPSC110FLMQB SCANPSC110F
Text: SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port IEEE1149.1 System Test Support General Description Features The SCANPSC110F Bridge extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a hierarchical approach over a single serial scan chain is
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SCANPSC110F
IEEE1149
SCANPSC110F
lfsr16
SCANPSC110FFMQB
SCANPSC110FLMQB
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64 CERAMIC LEADLESS CHIP CARRIER LCC
Abstract: C1996 SCANPSC110F SCANPSC110FDMQB SCANPSC110FFMQB SCANPSC110FLMQB SCANPSC110FSC SCANPSC110FSCX
Text: SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port IEEE1149 1 System Test Support General Description Features The SCANPSC110F Bridge extends the IEEE Std 1149 1 test bus into a multidrop test bus environment The advantage of a hierarchical approach over a single serial scan
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SCANPSC110F
IEEE1149
64 CERAMIC LEADLESS CHIP CARRIER LCC
C1996
SCANPSC110FDMQB
SCANPSC110FFMQB
SCANPSC110FLMQB
SCANPSC110FSC
SCANPSC110FSCX
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Untitled
Abstract: No abstract text available
Text: PRODUCT SPECIFICATION TITLE SERIAL ATA BACKPLANE CONNECTOR / 1.27mm PITCH 1.0 SCOPE This Product Specification covers the mechanical, electrical and environmental performances requirements and test methods for Serial-ATA connector series products. 2.0 APPLICABLE DOCUMENTS AND SPECIFICATIONS
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50-durability
500durability
SH2009-0536
PS-67492-001
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Untitled
Abstract: No abstract text available
Text: N4906B Serial BERT Data Sheet Version 3.0 New: Enhanced measurement suite Agilent Technologies N4900 Series The Agilent N4900 serial BERT series provides industry-leading parametric test capabilities for design verification, characterization and manufacturing of semiconductor and communication
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N4906B
N4900
N4903A
5989-2406EN
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SCANSTA112
Abstract: SCANSTA111 SCANPSC110 STA112
Text: SCANSTA112 7-Port Multidrop IEEE 1149.1 JTAG Multiplexer General Description Features The SCANSTA112 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board
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SCANSTA112
SCANSTA112
IEEE1149
CSP-9-111S2)
CSP-9-111S2.
SCANSTA111
SCANPSC110
STA112
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SCANSTA112
Abstract: STA112 A001 A101 SCANPSC110 SCANSTA111 SCANport
Text: SCANSTA112 7-port Multidrop IEEE 1149.1 JTAG Multiplexer General Description The SCANSTA112 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board
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SCANSTA112
SCANSTA112
IEEE1149
STA112
A001
A101
SCANPSC110
SCANSTA111
SCANport
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SCANSTA111
Abstract: STA112 a0b1 A001 SCANPSC110 SCANSTA112 A101 diode SCANSTA112SM/NOPB
Text: SCANSTA112 7-port Multidrop IEEE 1149.1 JTAG Multiplexer General Description The SCANSTA112 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board
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SCANSTA112
SCANSTA112
IEEE1149
SCANSTA111
STA112
a0b1
A001
SCANPSC110
A101 diode
SCANSTA112SM/NOPB
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Untitled
Abstract: No abstract text available
Text: Agilent E5910A Serial Link Optimizer for Xilinx FPGAs Data Sheet Automatically tune your MGT-based serial links for optimal performance Agilent Technologies and Xilinx have combined tools and technology to create a powerful test and analysis solution focused
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E5910A
5989-6048EN
5989-5969EN
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