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    SERIAL PERIPHERAL INTERFACE SPI Search Results

    SERIAL PERIPHERAL INTERFACE SPI Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TB67S539FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=2/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S141AFTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=84/Iout(A)=3/Phase Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S149AFTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=84/Iout(A)=3/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S549FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=1.5/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    DCL541A01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: Low / Input disable Visit Toshiba Electronic Devices & Storage Corporation

    SERIAL PERIPHERAL INTERFACE SPI Datasheets (1)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    Serial Peripheral Interface (SPI) Atmel 32-bit Embedded ASIC Core Peripheral Original PDF

    SERIAL PERIPHERAL INTERFACE SPI Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    verilog code for slave SPI with FPGA

    Abstract: vhdl spi interface VHDL code for slave SPI with FPGA
    Text: SPI_MS Serial Peripheral Interface Master/Slave Core The Serial Peripheral Interface SPI allows high-speed synchronous serial data transfers between microprocessors, microcontrollers and peripheral devices. The SPI_MS core implements the Serial Peripheral Interface, which can operate either


    Original     		PDF

    verilog code for slave SPI with FPGA

    Abstract: EP1C3T100C8 vhdl spi interface vhdl spi bus VHDL code for slave SPI with FPGA "Serial peripheral interface" vhdl synchronous bus vhdl code for 8 bit shift register verilog code for 64 32 bit register
    Text: SPI_MS Serial Peripheral Interface Master/Slave Altera Core The Serial Peripheral Interface SPI allows high-speed synchronous serial data transfers between microprocessors, microcontrollers and peripheral devices. The SPI_MS core implements the Serial Peripheral Interface, which can operate either


    Original     		PDF

    spi flash controller

    Abstract: 04H0000 simple spi flash "Serial peripheral interface" 0X03H 0X02H
    Text: Designing a Serial Peripheral Interface Application Note by Eric Lin 1. What is a Serial Peripheral Interface SPI ? A serial peripheral interface (SPI) has a simple 4-wire synchronous interface protocol that enables controllers and peripheral devices to intercommunicate.


    Original     		PDF

    nanotron

    Abstract: 802.15.4a Nanotron Technologies NanoNET nanoNET Register spi slave SPI protocol Chirp Spread Spectrum nanoNET SPI DSA001264
    Text: nanoNET Serial Peripheral Interface Specifications Version 1.06 NA-02-0151-0128-1.06 Document Information nanoNET Serial Peripheral Interface Specifications Document Information Document Title: nanoNET Serial Peripheral Interface Specifications Document Version:


    Original     		PDF NA-02-0151-0128-1 nanotron 802.15.4a Nanotron Technologies NanoNET nanoNET Register spi slave SPI protocol Chirp Spread Spectrum nanoNET SPI DSA001264

    xc6vlx130t-ff1156

    Abstract: XILINX ipic axi
    Text: LogiCORE IP AXI Serial Peripheral Interface AXI SPI (v1.02.a) DS742 January 18, 2012 Product Specification Introduction LogiCORE IP Facts The AXI Serial Peripheral Interface (SPI) connects to the Advanced eXtensible Interface (AXI4). This core provides a serial interface to SPI devices such as SPI


    Original     		PDF DS742 M68HC11 32-bit xc6vlx130t-ff1156 XILINX ipic axi

    mst 718 BE

    Abstract: MST 718 PB10 PB12 PC10 spi In Circuit Serial Programming
    Text: SECTION 7 SERIAL PERIPHERAL INTERFACE DSP56L811 User’s Manual 7-1 Serial Peripheral Interface 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7-2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 SPI ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5


    Original     		PDF DSP56L811 mst 718 BE MST 718 PB10 PB12 PC10 spi In Circuit Serial Programming

    XC5VLX50-FF676

    Abstract: XC4VFX12-FF668-10 xc5vlx50-ff676-1 XC6VLX130TFF1156 XC3S700A VIRTEX-5 DDR2 controller DS570 AT45DB161D M25P16 PLBV46
    Text: XPS Serial Peripheral Interface SPI (v2.01b) DS570 September 16, 2009 Product Specification 0 0 Introduction LogiCORE Facts The XPS Serial Peripheral Interface (SPI) connects to the PLB V4.6 (Processor Local Bus with Xilinx simplifications) and provides a serial interface to SPI


    Original     		PDF DS570 M68HC11 XC5VLX50-FF676 XC4VFX12-FF668-10 xc5vlx50-ff676-1 XC6VLX130TFF1156 XC3S700A VIRTEX-5 DDR2 controller AT45DB161D M25P16 PLBV46

    AN-485-1

    Abstract: EPM240 "1 wire slave interface" verilog verilog code for 8 bit shift register # 6 6 0 8 spi interface
    Text: Serial Peripheral Interface Master in MAX II CPLDs Application Note 485 December 2007, version 1.0 Introduction The serial peripheral interface SPI is a widely used, 4-wire, serial communication interface. Applications such as digital audio, digital signal processing, and telecommunication channels require high-speed


    Original     		PDF

    MPC5554 Application note

    Abstract: AN2847 AN2864 MCF5235 MPC5500 MPC5554 MPC5500 Configuration
    Text: Freescale Semiconductor Application Note Using the Serial Peripheral Interface SPI eTPU Function by: Jenifer Scott & Geoff Emerson Freescale 32-Bit Embedded Controller Division This eTPU Serial Peripheral Interface (SPI) application note is intended to provide simple C interface functions


    Original     		PDF 32-Bit MPC5554 MCF5235 AN2864, AN2847 MPC5554 Application note AN2847 AN2864 MPC5500 MPC5500 Configuration

    Untitled

    Abstract: No abstract text available
    Text: Preliminary Datasheet R1EX25512ASA00I R1EX25512ATA00I Serial Peripheral Interface 512K EEPROM 64-Kword x 8-bit R10DS0044EJ0100 Rev.1.00 Oct.04, 2010 Description R1EX25xxx series is the Serial Peripheral Interface compatible (SPI) EEPROM (Electrically Erasable and


    Original     		PDF R1EX25512ASA00I R1EX25512ATA00I 64-Kword R10DS0044EJ0100 R1EX25xxx 128-byte

    PRSP0008DF-B

    Abstract: R1EX25512ASA00I
    Text: Preliminary Datasheet R1EX25512ASA00I R1EX25512ATA00I Serial Peripheral Interface 512K EEPROM 64-Kword x 8-bit R10DS0044EJ0100 Rev.1.00 Oct.04, 2010 Description R1EX25xxx series is the Serial Peripheral Interface compatible (SPI) EEPROM (Electrically Erasable and


    Original     		PDF R1EX25512ASA00I R1EX25512ATA00I 64-Kword R10DS0044EJ0100 R1EX25xxx 128-byte PRSP0008DF-B R1EX25512ASA00I

    N25Q256

    Abstract: WINBOND W25Q80 XC7K325TFFG900 XC6VLX130TFF1156 W25Q64VSFIG XC7K325T W25Q64vs axi4 DS843 W25Q80
    Text: LogiCORE IP AXI Quad Serial Peripheral Interface AXI Quad SPI (v1.00a) DS843 October 19, 2011 Product Specification Introduction LogiCORE IP Facts The AXI Quad Serial Peripheral Interface connects the AXI4 interface to SPI slave devices that support the


    Original     		PDF DS843 M68HC11 N25Q256 WINBOND W25Q80 XC7K325TFFG900 XC6VLX130TFF1156 W25Q64VSFIG XC7K325T W25Q64vs axi4 W25Q80

    Untitled

    Abstract: No abstract text available
    Text: Preliminary Datasheet R1EX25512ASA00A R1EX25512ATA00A Serial Peripheral Interface 512K EEPROM 64-Kword x 8-bit R10DS0046EJ0200 Rev.2.00 Oct.04, 2010 Description R1EX25xxx series is the Serial Peripheral Interface compatible (SPI) EEPROM (Electrically Erasable and


    Original     		PDF R1EX25512ASA00A R1EX25512ATA00A 64-Kword R10DS0046EJ0200 R1EX25xxx 128-byte R9044

    R1EX25512ASA00A

    Abstract: PRSP0008DF-B R1EX25512ATA00A
    Text: Preliminary Datasheet R1EX25512ASA00A R1EX25512ATA00A Serial Peripheral Interface 512K EEPROM 64-Kword x 8-bit R10DS0046EJ0200 Rev.2.00 Oct.04, 2010 Description R1EX25xxx series is the Serial Peripheral Interface compatible (SPI) EEPROM (Electrically Erasable and


    Original     		PDF R1EX25512ASA00A R1EX25512ATA00A 64-Kword R10DS0046EJ0200 R1EX25xxx 128-byte Re9044 R1EX25512ASA00A PRSP0008DF-B R1EX25512ATA00A

    25C020

    Abstract: No abstract text available
    Text: 2 Kbit 256 x 8 bit Serial CMOS EEPROMs, Serial Peripheral Interface (SPI) Synchronous Bus SLx 25C020 Preliminary Features • Serial peripheral interface (SPI) compatible, supports SPI Modes 0,0 and 1,1 • Page Protection ModeTM for protecting the EEPROM against unintended data changes


    Original     		PDF 25C020 25C020. 25C020

    25C080

    Abstract: No abstract text available
    Text: 8 Kbit 1024 x 8 bit Serial CMOS EEPROMs, Serial Peripheral Interface (SPI) Synchronous Bus SLx 25C080 Preliminary Features • Serial peripheral interface (SPI) compatible, supports SPI Modes 0,0 and 1,1 • Page Protection ModeTM for protecting the EEPROM against unintended data changes


    Original     		PDF 25C080 25C080. 32-byte 25C080

    SST89x5xxRDX

    Abstract: master-slave 8051 SN74LVC4245A SST25VF010 LF30CV stmicroelectronics superflash SST25VF020 F2051
    Text: FlashFlex Microcontroller Single Master, Multi-Slave Serial Peripheral Interface Application Note August 2008 FlashFlex MCU: Single Master, Multi-Slave Serial Peripheral Interface 1.0 INTRODUCTION 2.0 HARDWARE The SPI protocol is a widely accepted and easily used


    Original     		PDF 0000h S72051-03-000 SST89x5xxRDX master-slave 8051 SN74LVC4245A SST25VF010 LF30CV stmicroelectronics superflash SST25VF020 F2051

    master-slave 8051

    Abstract: LF30CV SST25VF010 SST25VF020 F2051 FLASHFLEX51 memory chip microcontroller schematic
    Text: FlashFlex51 Microcontroller Single Master, Multi-Slave Serial Peripheral Interface Application Note June 2003 FlashFlex51 MCU: Single Master, Multi-Slave Serial Peripheral Interface 1.0 INTRODUCTION 2.0 HARDWARE The SPI protocol is a widely accepted and easily used


    Original     		PDF FlashFlex51 0000h S72051-01-000 master-slave 8051 LF30CV SST25VF010 SST25VF020 F2051 memory chip microcontroller schematic

    25C160

    Abstract: No abstract text available
    Text: 16 Kbit 2048 x 8 bit Serial CMOS EEPROMs, Serial Peripheral Interface (SPI) Synchronous Bus SLx 25C160 Preliminary Features • Serial peripheral interface (SPI) compatible, supports SPI Modes 0,0 and 1,1 • Page Protection ModeTM for protecting the EEPROM against unintended data changes


    Original     		PDF 25C160 25C160. 32-byte 25C160

    25c010

    Abstract: No abstract text available
    Text: 1 Kbit 128 x 8 bit Serial CMOS EEPROMs, Serial Peripheral Interface (SPI) Synchronous Bus SLx 25C010 Preliminary Features • Serial peripheral interface (SPI) compatible, supports SPI Modes 0,0 and 1,1 • Page Protection ModeTM for protecting the EEPROM against unintended data changes


    Original     		PDF 25C010 25C010. 25c010

    25c040

    Abstract: Serial Peripheral Interface
    Text: 4 Kbit 512 x 8 bit Serial CMOS EEPROMs, Serial Peripheral Interface (SPI) Synchronous Bus SLx 25C040 Preliminary Features • Serial peripheral interface (SPI) compatible, supports SPI Modes 0,0 and 1,1 • Page Protection ModeTM for protecting the EEPROM against unintended data changes


    Original     		PDF 25C040 25C040. 25c040 Serial Peripheral Interface

    68hc11 multiple byte transfer using spi

    Abstract: VHDL code for slave SPI with FPGA 68HC11 DS210 M68HC11 MC68HC11 baud rate generator vhdl vhdl code for spi
    Text: OPB Serial Peripheral Interface SPI DS210 (v2.2) July 23, 2002 Summary Product Specification This document presents specifications for the VHDL implementation of Motorola’s Serial Peripheral Interface (SPI) in a Xilinx FPGA. The original specifications closely followed


    Original     		PDF DS210 M68HC11-Rev. M68HC11 Periph8260 68hc11 multiple byte transfer using spi VHDL code for slave SPI with FPGA 68HC11 DS210 MC68HC11 baud rate generator vhdl vhdl code for spi

    EB275

    Abstract: FC15 M68HC05 M68HC11 DSA003656
    Text: Order this document by EB275/D Motorola Semiconductor Engineering Bulletin EB275 Example Using the Queued Serial Peripheral Interface on Modular MCUs By Sharon Darley Austin, Texas Introduction The QSPI queued serial peripheral interface uses a synchronous serial


    Original     		PDF EB275/D EB275 M68HC11 M68HC05 EB275 FC15 DSA003656

    M68HC05

    Abstract: M68HC11 MC68332 MC68341
    Text: SECTION 9 QUEUED SERIAL PERIPHERAL MODULE The queued serial peripheral module QSPM provides a queued serial peripheral interface (QSPI). The QSPI is a full-duplex, synchronous serial interface for communicating with peripherals or microprocessors. It is enhanced by the addition of a


    OCR Scan     		PDF MC68341 M68HC05 M68HC11 MC68332