SDRAM U221 Search Results

SDRAM U221 Result Highlights (5)

Part	Manufacturer	Description
HM2P09PDU221N9LF	Amphenol Communications Solutions	Back Plane Connectors,2mm Hard Metric Series,Millipacs, Vertical Header, Type C with peg 2.5mm, 55 Signal Pin, Press Fit Tail,Shielded, 250 mating cycles and ROHS Compliant
HM2P09PDU221N2LF	Amphenol Communications Solutions	Millipacs®, Back Plane Connectors, 2mm Hard Metric Series 5 Row vertical Press-Fit Header, Type C with 55 Signal Pins and RoHS compatable
CSPT857CNLG	Renesas Electronics Corporation	2.5V - 2.6V PLL Differential 1:10 SDRAM Clock Driver
CSPT857DPAG	Renesas Electronics Corporation	2.5V-2.6V Phase Locked Loop Differential 1:10 SDRAM Clock Driver
CSPU877DBVG	Renesas Electronics Corporation	1.8V Phase Locked Loop Differential 1:10 SDRAM Clock Driver

SDRAM U221 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
Untitled Abstract: No abstract text available Text: PCS2I2310ANZ Product Preview 3.3 V SDRAM Buffer for Mobile PCS with 4 SO-DIMMs http://onsemi.com Description The PCS2I2310ANZ is a 3.3 V buffer designed to distribute high−speed clocks in mobile PC applications. The part has 10 outputs, 8 of which can be used to drive up to four SDRAM SO−DIMMs, and	Original	PDF	PCS2I2310ANZ PCS2I2310ANZ PCS2I2310ANZ/D
Hitachi DSA00171 Abstract: No abstract text available Text: HM5212165 シリ−ズ HM5212805 シリ−ズ 128M LVTTL interface SDRAM 66 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank ADJ-203-289A Z ’98. 7.1 Rev. 1.0 概要 HM5212165 シリーズは，2097152 ワード × 16 ビット × 4 バンク構成の SDRAM です。HM5212805 シリー	Original	PDF	HM5212165 HM5212805 16-bit ADJ-203-289A HM5212805 HM5212805) HM5212165) /64ms Hitachi DSA00171
DDR400B Abstract: E1202 Text: DATA SHEET 128M bits DDR SDRAM EDD1232ACBH 4M words x 32 bits Features • Density: 128M bits • Organization  1M words × 32 bits × 4 banks • Package: 144-ball FBGA  Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD, VDDQ = 2.5V −0.125V/+0.2V	Original	PDF	EDD1232ACBH 144-ball 400Mbps M01E0706 E1202E20 DDR400B E1202
48-PIN Abstract: CDC318A Text: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	PDF	CDC318A 18LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin CDC318A
ADSP-TS201S Abstract: AD1854 AD1871 ADDS-TS201S-EZLITE Text: ADSP-TS201S EZ-KIT Lite Evaluation Kit for the TigerSHARC Processor Key Features • Dual ADSP-TS201S TigerSHARC Processors • 4 MB 512k  8-bit flash memory • 32 MB (4M  64-bit) SDRAM • AD1871, stereo audio, 24-bit, 96 kHz, multibit, ∑–∆ ADC	Original	PDF	ADSP-TS201S 64-bit) D1871, 24-bit, D1854, 14-pin 90-pin PH04337-1 AD1854 AD1871 ADDS-TS201S-EZLITE
DDR400B Abstract: No abstract text available Text: DATA SHEET 128M bits DDR SDRAM EDD1232ACBH 4M words x 32 bits Specifications Features • Density: 128M bits • Organization  1M words × 32 bits × 4 banks • Package: 144-ball FBGA  Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD, VDDQ = 2.5V −0.125V/+0.2V	Original	PDF	EDD1232ACBH 144-ball 400Mbps M01E0706 E1202E20 DDR400B
Untitled Abstract: No abstract text available Text: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	PDF	CDC318A SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin
Untitled Abstract: No abstract text available Text: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	PDF	CDC318A 18LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin
48-PIN Abstract: CDC318A CDC318ADL CDC318ADLG4 CDC318ADLR Text: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	PDF	CDC318A 18LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin CDC318A CDC318ADL CDC318ADLG4 CDC318ADLR
ADSP-TS201S Abstract: AD1871 ADSP-TS201S EZ-KIT Lite Evaluation Kit AD1854 ADDS-TS201S-EZLITE tigersharc in audio system tigersharc Text: ADSP-TS201S EZ-KIT Lite Evaluation Kit for the TigerSHARC Processor Key Features • Dual ADSP-TS201S TigerSHARC Processors • 4 MB 512K ϫ 8-bit FLASH memory • 32 MB (4M ϫ 64-bit) SDRAM • AD1871, stereo audio, 24-bit, 96 kHz, multi-bit, ∑–∆ ADC	Original	PDF	ADSP-TS201S 64-bit) AD1871, 24-bit, AD1854, 14-pin 90-pin F-92182 AD1871 ADSP-TS201S EZ-KIT Lite Evaluation Kit AD1854 ADDS-TS201S-EZLITE tigersharc in audio system tigersharc
Untitled Abstract: No abstract text available Text: CDC2510B 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D D this Device Designed to Meet PC SDRAM Registered DIMM Specification Spread Spectrum Clock Compatible	Original	PDF	CDC2510B SCAS612 CDCVF2510A 24-Pin
PC133 registered reference design Abstract: No abstract text available Text: CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9	Original	PDF	CDCF2510 SCAS628D CDCVF2510A PC133 24-Pin PC133 registered reference design
PC133 registered reference design Abstract: CDC2509 Text: CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9	Original	PDF	CDCF2510 SCAS628D CDCVF2510A PC133 24-Pin PC133 registered reference design CDC2509
Untitled Abstract: No abstract text available Text: CDC2509B 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D D D D D D D D this Device Designed to Meet PC SDRAM Registered DIMM Specification Spread Spectrum Clock Compatible	Original	PDF	CDC2509B SCAS613C CDCVF2509A 24-Pin

Untitled Abstract: No abstract text available Text: CDC2510B 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D D this Device Designed to Meet PC SDRAM Registered DIMM Specification Spread Spectrum Clock Compatible	Original	PDF	CDC2510B SCAS612 CDCVF2510A 24-Pin
Untitled Abstract: No abstract text available Text: CDC2509B 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D D D D D D D D this Device Designed to Meet PC SDRAM Registered DIMM Specification Spread Spectrum Clock Compatible	Original	PDF	CDC2509B SCAS613C CDCVF2509A 24-Pin
PC133 registered reference design Abstract: CDC2509 Text: CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9	Original	PDF	CDCF2510 SCAS628D CDCVF2510A PC133 24-Pin PC133 registered reference design CDC2509
PC133 registered reference design Abstract: No abstract text available Text: CDCVF2509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS637C − DECEMBER 1999 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D D D D D D D D this Device Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1	Original	PDF	CDCVF2509 SCAS637C CDCVF2509A PC133 24-Pin PC133 registered reference design
PC133 registered reference design Abstract: No abstract text available Text: CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9	Original	PDF	CDCF2510 SCAS628D CDCVF2510A PC133 24-Pin PC133 registered reference design
N5208 Abstract: A114 A115 JESD22 JESD78 NCP5208 NCP5208DR2 Text: NCP5208 DDR−I/II Termination Regulator The NCP5208 is a linear regulator specifically designed for the active termination of DDR−I/II SDRAM. The device can be operated from a single supply voltage as low as 1.7 V. For DDR−I applications, the device is capable of sourcing and sinking current up	Original	PDF	NCP5208 NCP5208 NCP5208/D N5208 A114 A115 JESD22 JESD78 NCP5208DR2
CDC2510B Abstract: CDC2510BPWR CDCVF2510A CLY 70 Text: CDC2510B 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D D this Device Designed to Meet PC SDRAM Registered DIMM Specification Spread Spectrum Clock Compatible	Original	PDF	CDC2510B SCAS612 CDCVF2510A 24-Pin CDC2510B CDC2510BPWR CLY 70
PC133 registered reference design Abstract: No abstract text available Text: CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9	Original	PDF	CDCF2510 SCAS628D CDCVF2510A PC133 24-Pin PC133 registered reference design
PC133 registered reference design Abstract: No abstract text available Text: CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9	Original	PDF	CDCF2510 SCAS628D CDCVF2510A PC133 24-Pin PC133 registered reference design
PC133 registered reference design Abstract: No abstract text available Text: CDCF2509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS624C − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9	Original	PDF	CDCF2509 SCAS624C CDCVF2509A PC133 24-Pin PC133 registered reference design

SDRAM U221 Search Results

SDRAM U221 Result Highlights (5)

SDRAM U221 Datasheets Context Search

Untitled

Hitachi DSA00171

DDR400B

48-PIN

ADSP-TS201S

DDR400B

Untitled

Untitled

48-PIN

ADSP-TS201S

Untitled

PC133 registered reference design

PC133 registered reference design

Untitled

Untitled

Untitled

PC133 registered reference design

PC133 registered reference design

PC133 registered reference design

N5208

CDC2510B

PC133 registered reference design

PC133 registered reference design

PC133 registered reference design