LV86A
Abstract: No abstract text available
Text: SN54LV86A, SN74LV86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCLS392C – APRIL 1998 – REVISED JANUARY 2001 D D D D SN54LV86A . . . J OR W PACKAGE SN74LV86A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)
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SN54LV86A,
SN74LV86A
SCLS392C
000-V
A114-A)
A115-A)
SN54LV86A
SN74LV86A
LV86A
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A115-A
Abstract: C101 SN54LV86A SN74LV86A
Text: SN54LV86A, SN74LV86A QUADRUPLE 2ĆINPUT EXCLUSIVEĆOR GATES SCLS392F − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8 ns at 5 V D Typical VOLP Output Ground Bounce D D D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)
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SN54LV86A,
SN74LV86A
SCLS392F
000-V
A114-A)
A115-A)
SN54LV86A
A115-A
C101
SN54LV86A
SN74LV86A
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A115-A
Abstract: C101 SN54LV86A SN74LV86A
Text: SN54LV86A, SN74LV86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCLS392D – APRIL 1998 – REVISED AUGUST 2003 D D D D SN54LV86A . . . J OR W PACKAGE SN74LV86A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Max tpd of 8 ns at 5 V Typical VOLP (Output Ground Bounce)
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Original
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SN54LV86A,
SN74LV86A
SCLS392D
SN54LV86A
000-V
A114-A)
A115-A)
A115-A
C101
SN54LV86A
SN74LV86A
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FT 4013 d dual flip flop
Abstract: FT 4013 D flip flop 74HC octal bidirectional latch 74HCT 4013 DATASHEET 4511 pin configuration SN7432 fairchild CMOS TTL Logic Family Specifications 7805 acv Datasheet of decade counter CD 4017 sn74154
Text: T H E W O R L D L E A D E R I N L O G I C P R O D U C T S Logic Selection Guide February 2000 1999 EEProduct News PRODUCTS OF THE YEAR AWARD New products for prototype design AVC Advanced Very-Low-Voltage CMOS Logic See Section 4 LOGIC OVERVIEW 1 FUNCTIONAL INDEX
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