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    Abstract: No abstract text available
    Text: SN74LVC2G00 DUAL 2-INPUT POSITIVE-NAND GATE SCES193A – APRIL 1999 – REVISED JULY 1999 D D D D EPIC  Enhanced-Performance Implanted CMOS Process Ioff Feature Supports Partial-Power-Down Mode Operation Supports 5-V VCC Operation Packaged in Plastic Small-Outline


    Original     		PDF SN74LVC2G00 SCES193A