CDCLVD1204
Abstract: No abstract text available
Text: CDCLVD1204 www.ti.com SCAS898A – MAY 2010 – REVISED JUNE 2010 2:4 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1204 FEATURES DESCRIPTION • • The CDCLVD1204 clock buffer distributes one of two selectable clock inputs, IN0, IN1 , to 4 pairs of
|
Original
|
PDF
|
CDCLVD1204
SCAS898A
10-kHz
20-MHz
EAI/TIA-644A
16-Pin
CDCLVD1204
|
CDCLVD1204
Abstract: No abstract text available
Text: CDCLVD1204 www.ti.com SCAS898A – MAY 2010 – REVISED JUNE 2010 2:4 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1204 FEATURES DESCRIPTION • • The CDCLVD1204 clock buffer distributes one of two selectable clock inputs, IN0, IN1 , to 4 pairs of
|
Original
|
PDF
|
CDCLVD1204
SCAS898A
CDCLVD1204
10-kHz
20-MHz
|
CDCLVD1204
Abstract: No abstract text available
Text: CDCLVD1204 www.ti.com SCAS898A – MAY 2010 – REVISED JUNE 2010 2:4 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1204 FEATURES DESCRIPTION • • The CDCLVD1204 clock buffer distributes one of two selectable clock inputs, IN0, IN1 , to 4 pairs of
|
Original
|
PDF
|
CDCLVD1204
SCAS898A
10-kHz
20-MHz
EAI/TIA-644A
16-Pin
CDCLVD1204
|
CDCLVD1204
Abstract: No abstract text available
Text: CDCLVD1204 www.ti.com SCAS898A – MAY 2010 – REVISED JUNE 2010 2:4 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1204 FEATURES DESCRIPTION • • The CDCLVD1204 clock buffer distributes one of two selectable clock inputs, IN0, IN1 , to 4 pairs of
|
Original
|
PDF
|
CDCLVD1204
SCAS898A
10-kHz
20-MHz
EAI/TIA-644A
16-Pin
CDCLVD1204
|
CDCLVD1204
Abstract: No abstract text available
Text: CDCLVD1204 www.ti.com SCAS898A – MAY 2010 – REVISED JUNE 2010 2:4 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1204 FEATURES DESCRIPTION • • The CDCLVD1204 clock buffer distributes one of two selectable clock inputs, IN0, IN1 , to 4 pairs of
|
Original
|
PDF
|
CDCLVD1204
SCAS898A
CDCLVD1204
10-kHz
20-MHz
|
CDCLVD1204
Abstract: No abstract text available
Text: CDCLVD1204 www.ti.com SCAS898A – MAY 2010 – REVISED JUNE 2010 2:4 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1204 FEATURES DESCRIPTION • • The CDCLVD1204 clock buffer distributes one of two selectable clock inputs, IN0, IN1 , to 4 pairs of
|
Original
|
PDF
|
CDCLVD1204
SCAS898A
10-kHz
20-MHz
EAI/TIA-644A
16-Pin
CDCLVD1204
|