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    Abstract: No abstract text available
    Text: CDCV850 2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE SCAS647C − OCTOBER 2000 − REVISED MARCH 2013 D Phase-Lock Loop Clock Driver for Double D D D D D D D D D Data-Rate Synchronous DRAM Applications Spread Spectrum Clock Compatible Operating Frequency: 60 to 140 MHz


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    PDF CDCV850 SCAS647C 48-Pin