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    CDC2509

    Abstract: CDC2509PWR
    Text: CDC2509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS580A – OCTOBER 1996 – REVISED JANUARY 1998 D D D D D D D D PW PACKAGE TOP VIEW Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs


    Original     		PDF CDC2509 SCAS580A 24-Pin CDC2509 CDC2509PWR

    CDC2509

    Abstract: No abstract text available
    Text: CDC2509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS580A - OCTOBER 1996 - REVISED JANUARY 1998 Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output


    OCR Scan     		PDF CDC2509 SCAS580A 24-Pin