74LVT
Abstract: 74LVT20 74LVT20PW
Text: INTEGRATED CIRCUITS 74LVT20 3.3V Dual 4-input NAND gate Product specification IC24 Data Handbook Philips Semiconductors 1996 Aug 28 Philips Semiconductors Product specification 3.3V Dual 4-input NAND gate 74LVT20 QUICK REFERENCE DATA SYMBOL LOGIC DIAGRAM CONDITIONS
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74LVT20
SA00352
74LVT
74LVT20
74LVT20PW
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DNA SMD MARKING CODE
Abstract: No abstract text available
Text: INTEGRATED CIRCUITS 74LVT20 3.3V Dual 4-input NAND gate Product specification IC24 Data Handbook Philips Semiconductors 1996 Aug 28 Philips Semiconductors Product specification 3.3V Dual 4-input NAND gate 74LVT20 QUICK REFERENCE DATA SYMBOL LOGIC DIAGRAM CONDITIONS
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74LVT20
74LVT20
SA00352
01-Jan-98)
DNA SMD MARKING CODE
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SOT108-1
Abstract: Philips Semiconductors 74ABT 74ABT20 74ABT20PW
Text: INTEGRATED CIRCUITS 74ABT20 Dual 4-input NAND gate Product specification IC23 Data Handbook Philips Semiconductors 1995 Sep 22 Philips Semiconductors Product specification Dual 4-input NAND gate 74ABT20 QUICK REFERENCE DATA SYMBOL tPLH tPHL LOGIC DIAGRAM CONDITIONS
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74ABT20
SOT108-1
Philips Semiconductors
74ABT
74ABT20
74ABT20PW
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74ABT
Abstract: 74ABT20 74ABT20PW
Text: Philips Semiconductors Product specification Dual 4-input NAND gate 74ABT20 QUICK REFERENCE DATA SYMBOL tPLH tPHL LOGIC DIAGRAM CONDITIONS Tamb = 25°C; GND = 0V PARAMETER Propagation delay An, Bn, Cn, Dn to Yn TYPICAL A0 B0 CL = 50pF; VCC = 5V tOSLH tOSHL
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74ABT20
SA00352
74ABT
500ns
SH00067
74ABT
74ABT20
74ABT20PW
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74LVT20
Abstract: 74LVT20D 74LVT20PW
Text: Philips Semiconductors Product specification 3.3V Dual 4-input NAND gate 74LVT20 QUICK REFERENCE DATA CONDITIONS Tamb = 25°C; GND = OV PARAMETER SYMBOL LOGIC DIAGRAM tPLH tpHL Propagation delay An, Bn, Cn, Dn to Yn CL = 50pF; VCC = 3.3V C|N Input capacitance
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74LVT20
SA00351
SQT402-1
MO-153
7110fl2b
74LVT20
74LVT20D
74LVT20PW
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Untitled
Abstract: No abstract text available
Text: Philips Semiconductors Product specification Dual 4-input NAND gate 74ABT20 QUICK REFERENCE DATA SYMBOL PARAMETER Propagation delay An, Bn, Cn, Dn to Yn tpLH tpHL LOGIC DIAGRAM CONDITIONS Tamb = 25°C; GND = OV TYPICAL Cl = 50pF; VCC = 5V 5 Ï CO CO «9*9
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74ABT20
1995S
MO-153
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74ABT20
Abstract: 74ABT20D 74ABT20N 74ABT20PW TPL 762 JF
Text: Philips Semiconductors Product specification Dual 4-input NAND gate 74ABT20 QUICK REFERENCE DATA LOGIC DIAGRAM CONDITIONS Tamb = 25°C; GND = 0V SYMBOL PARAMETER tpLH tpHL Propagation delay An, Bn, Cn, Dn to Yn tOSLH *OSHL Output to Output skew CiN Input capacitance
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74ABT20
SA00351
SQT402-1
MO-153
74ABT20
74ABT20D
74ABT20N
74ABT20PW
TPL 762 JF
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