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    40B5

    Abstract: 42B2 RT54SX-S TQ100
    Text: v4.1 eX Family FPGAs FuseLock Leading Edge Performance • • • • • 240 MHz System Performance 350 MHz Internal Performance 3.9 ns Clock-to-Out Pad-to-Pad • • • Specifications • • • • • 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops (Using CC Macros)


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    Silicon Sculptor II

    Abstract: 40B5 42B2 RT54SX-S TQ100 180-pin
    Text: v4.3 eX Family FPGAs FuseLock Leading Edge Performance • • • • • 240 MHz System Performance 350 MHz Internal Performance 3.9 ns Clock-to-Out Pad-to-Pad • • • Specifications • • • • • 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops (Using CC Macros)


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    HiRel a54sx72a unused

    Abstract: No abstract text available
    Text: Advanced v1.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10


    Original     		PDF RT54SX-S RT54SX-S TM1019 HiRel a54sx72a unused

    rt54sx32su

    Abstract: RTSX72 RTSX32SU RTSX72-S
    Text: Advanced v0.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		PDF TM1019 rt54sx32su RTSX72 RTSX32SU RTSX72-S

    Pin Compatibility Allows Prototyping with Commercial SX-A FPGAs

    Abstract: RT54SX72S-CQ256 RTSX32S
    Text: Advanced v 0.1.1 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <


    Original     		PDF RT54SX-S 100krad RT54SX-S Pin Compatibility Allows Prototyping with Commercial SX-A FPGAs RT54SX72S-CQ256 RTSX32S

    Untitled

    Abstract: No abstract text available
    Text: v2 . 1 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		PDF TM1019

    sx08a

    Abstract: No abstract text available
    Text: v4.0  SX-A Family FPGAs u e Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5V PCI, 5V TTL, 3.3V LVTTL, 2.5V LVCMOS2 • 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input Tolerance and 5V Drive Strength • Devices Support Multiple Temperature Grades


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    TM101

    Abstract: No abstract text available
    Text: Advanced v1.2.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate < 10–10


    Original     		PDF RT54SX-S 100krad RT54SX-S TM1019 TM101

    RTSX32su

    Abstract: Actel a54sx72a tid Silicon Sculptor II
    Text: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		PDF TM1019 RTSX32su Actel a54sx72a tid Silicon Sculptor II

    A54SX16A

    Abstract: No abstract text available
    Text: v4.0  SX-A Family FPGAs u e Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5V PCI, 5V TTL, 3.3V LVTTL, 2.5V LVCMOS2 • 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input Tolerance and 5V Drive Strength • Devices Support Multiple Temperature Grades


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    RTSX32su

    Abstract: RTSX32SU CQ84 RTSX72SU
    Text: v2.0 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		PDF TM1019 RTSX32su RTSX32SU CQ84 RTSX72SU

    types of trees in data structure

    Abstract: AC198 A54SXA RT54SX-S timing analysis example Signal Path Designer RTAX-S library
    Text: Application Note AC198 Clock Skew and Short Paths Timing Clock Skew Differences in clock signal arrival times across the chip are called clock skew. It is a fundamental design principle that timing must satisfy register setup and hold time requirements. Both data propagation delay


    Original     		PDF AC198 types of trees in data structure AC198 A54SXA RT54SX-S timing analysis example Signal Path Designer RTAX-S library

    Untitled

    Abstract: No abstract text available
    Text: Advanced v0.1.1 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <


    Original     		PDF RT54SX-S 100krad

    Untitled

    Abstract: No abstract text available
    Text: v 2 .0 54SX Family FPGAs RadTolerant and HiRel Hig h D ens it y De vi ces Fe a t ur es • 16,000 and 32,000 Available Logic Gates Rad To ler ant 54S X Fam i ly • Tested Total Ionizing Dose TID Survivability Level • Up to 228 User I/Os • Radiation Performance to 100Krads (Si) (ICC Standby


    Original     		PDF 100Krads

    A54SX32A

    Abstract: A54SX72A PAR64 REQ64 RT54SX-S
    Text: Advanced v1.2 HiRel SX-A Family FPGAs L ea d i n g E dg e P e rf o rm an c e • Cold-Sparing Capability • 215 MHz System Performance Military Temperature • Slow Slew Rate Option • 5.3 ns Clock-to-Out (Pin-to-Pin) (Military Temperature) • QML Certified Devices


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    RT54SX72S

    Abstract: A54SX72A RT54SX-S Signal Path Designer
    Text: Techni c al Br i ef Using A54SX72A and RT54SX72S Quadrant Clocks Ar ch it e c tu r al Ov er vi ew The A54SX72A and RT54SX72S devices offer four quadrant clock networks QCLK0, 1, 2, and 3 that can be driven from external points or from internal logic signals within the


    Original     		PDF A54SX72A RT54SX72S RT54SX-S Signal Path Designer

    RTAX1000S-STD

    Abstract: fpga 1553B 1553b VHDL RTAX1000S V203M manchester verilog decoder MIL-STD-1553B FPGA vhdl code manchester encoder MIL-HDBK-1553A 553B
    Text: v2.0 MIL-STD-1553B Bus Controller Core1553BBC Pr od uc t S um m ary S ynt he si s and S im ul ati on S uppor t In t e n d e d Us e • Synthesis: Exemplar, Synplicity, Design Compiler, FPGA Compiler, FPGA Express • 1553B Bus Controller BC • DMA Backend Interface to External Memory


    Original     		PDF MIL-STD-1553B Core1553BBC 1553B MIL-STD-1553B 128kbytes Core1553BRT RTAX1000S-STD fpga 1553B 1553b VHDL RTAX1000S V203M manchester verilog decoder MIL-STD-1553B FPGA vhdl code manchester encoder MIL-HDBK-1553A 553B

    A54SX72* radiation

    Abstract: cg624 A54SX72A actel 1020 datasheet RT54SX72S RT54SX-S TM1019 HiRel a54sx72a unused
    Text: Advanced v1.4 RT54SX-S RadTolerant FPGAs for Space Applications S p ec i a l F e a tu r es fo r S p ac e • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10


    Original     		PDF RT54SX-S TM1019 A54SX72* radiation cg624 A54SX72A actel 1020 datasheet RT54SX72S RT54SX-S HiRel a54sx72a unused

    EX256-TQ100

    Abstract: No abstract text available
    Text: Revision 10 eX Family FPGAs Leading Edge Performance • 240 MHz System Performance • 350 MHz Internal Performance • 3.9 ns Clock-to-Out Pad-to-Pad Specifications • 3,000 to 12,000 Available System Gates • Maximum 512 Flip-Flops (Using CC Macros)


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    RT54SX72SCQ208

    Abstract: CQ208 AC195 SY-PQ208-2 A54SX72A-PQ208 ACTEL CCGA to FBGA Adapter RT54SX32SCQ208 RT54SX32S-CQ208 FG484 A54SX32APQ
    Text: Application Note AC195 Prototyping for the RTSX-S Enhanced Aerospace FPGA Introduction Actel provides radiation-tolerant FPGAs for space applications. However, since the enhanced environmental properties of radiation tolerant devices are not required during prototyping, inexpensive


    Original     		PDF AC195 RT54SX72SCQ208 CQ208 AC195 SY-PQ208-2 A54SX72A-PQ208 ACTEL CCGA to FBGA Adapter RT54SX32SCQ208 RT54SX32S-CQ208 FG484 A54SX32APQ

    54SX32A

    Abstract: 54SX72A ACTEL burn-in RT54SX72SCQ208 54SX32 AX54SX72A 54sx72a burn-in AC172 RT54SX32S-CQ208 A54SX72* radiation
    Text: Application Note AC172 Post-Programming Burn-In PPBI for Actel RT54SX-S and SX-A FPGAs A b s t r a ct A rc h i te c t ur e Burn-in (BI) for programmed Field Programmable Gate Arrays (FPGAs) is a growing concern in the space community. This application note addresses these concerns


    Original     		PDF AC172 RT54SX-S 54SX32A 54SX72A ACTEL burn-in RT54SX72SCQ208 54SX32 AX54SX72A 54sx72a burn-in AC172 RT54SX32S-CQ208 A54SX72* radiation

    ACTEL 1020B

    Abstract: 1010B 40MX 42MX A54SX72A AC207 RT54SX72S RH1020 actel 1020 RT54SX-S
    Text: Application Note AC207 Global Clock Networks in Actel Antifuse Devices System performance is one of the most important characteristics of a design. As a result, designers put a lot of effort into improving clock speed. Clock skew is often a limiting factor in attaining maximum


    Original     		PDF AC207 ACTEL 1020B 1010B 40MX 42MX A54SX72A AC207 RT54SX72S RH1020 actel 1020 RT54SX-S

    22B2 DIODE

    Abstract: A54SX08A A54SX16A A54SX32A A54SX72A PQ208 TQ100 TQ144 TQ176
    Text: v5.2 SX-A Family FPGAs u e Leading-Edge Performance • • • 250 MHz System Performance 350 MHz Internal Performance • • • Specifications • • • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops


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    Untitled

    Abstract: No abstract text available
    Text: Revision 5 ex Automotive Family FPGAs Specifications • 3,000 to 12,000 Available System Gates • Maximum 512 Flip-Flops Using CC Macros • 0.22 m CMOS Process Technology • Up to 132 User-Programmable I/O Pins Features • Live on Power-Up • No Power-Up/Down Sequence Required for Supply


    Original     		PDF