RS-232 JTAG MATRIX Search Results

RS-232 JTAG MATRIX Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
GMM AM08 Abstract: Manuale Tecnico BIBLIOGRAFIA In-System Programming bascom avr keyboard 4X4 com1 pony prog lcd 20x2 schema rs 232 program bascom avr Text: GMM AM08 grifo Mini Modulo AT mega 8L MANUALE TECNICO Via dell' Artigiano, 8/6 ® 40016 San Giorgio di Piano grifo Bologna ITALY E-mail: grifo@grifo.it http://www.grifo.it http://www.grifo.com Tel. +39 051 892.052 (r.a.) FAX: +39 051 893.661 ITALIAN TECHNOLOGY	Original		PDF
AMBA AXI verilog code Abstract: 0x00000000-0x7FFFFFFF AMBA AXI to AHB BUS Bridge verilog code AMBA AXI to APB BUS Bridge 0x12345678 axi to apb bridge verilog code for ahb bus matrix ltxc2v6000 PB11MPCore PB1176JZF-S Text: $SSOLFDWLRQ1RWH Example AXI design for a Logic Tile on top of AXI Versatile base boards Document number: ARM DAI 0151G Issued: June 2008 Copyright ARM Limited 2008 $SSOLFDWLRQ1RWH [	Original	0151G LT-XC4VLX100+ LT-XC5VLX330 PB11MPCore ARM11MPCore CT11MPCore AMBA AXI verilog code 0x00000000-0x7FFFFFFF AMBA AXI to AHB BUS Bridge verilog code AMBA AXI to APB BUS Bridge 0x12345678 axi to apb bridge verilog code for ahb bus matrix ltxc2v6000 PB11MPCore PB1176JZF-S	PDF
AMBA AXI to APB BUS Bridge vhdl code Abstract: PrimeCell AXI Configurable Interconnect PL300 Implementation Guide AMBA AXI to AhB BUS Bridge vhdl code PL081 AMBA AXI to AHB BUS Bridge verilog code axi wrapper 0x10018000 CT926EJ-S LF712 tsmc 0.18um Text: $SSOLFDWLRQ1RWH Using a CT7TDMI, CT926EJ-S or CT1136JF-S Core Tile with an Emulation Baseboard Document number: ARM DAI 0148D Issued: October 2007 Copyright ARM Limited 2007 $SSOLFDWLRQ1RWH	Original	CT926EJ-S CT1136JF-S 0148D AMBA AXI to APB BUS Bridge vhdl code PrimeCell AXI Configurable Interconnect PL300 Implementation Guide AMBA AXI to AhB BUS Bridge vhdl code PL081 AMBA AXI to AHB BUS Bridge verilog code axi wrapper 0x10018000 LF712 tsmc 0.18um	PDF
RTSX32SU CQ84 Abstract: Silicon Sculptor II RTSX32SU actel 1020 Text: v2.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case	Original	TM1019 RTSX32SU CQ84 Silicon Sculptor II RTSX32SU actel 1020	PDF
RTSX32SU Abstract: RTSX32SU CQ84 Actel a54sx72a tid RTSX72SU RTSX-SU actel 1020 Silicon Sculptor II actel 1020 datasheet RT54SX E11213 Text: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case	Original	TM1019 RTSX32SU RTSX32SU CQ84 Actel a54sx72a tid RTSX72SU RTSX-SU actel 1020 Silicon Sculptor II actel 1020 datasheet RT54SX E11213	PDF
RTSX32su Abstract: Actel a54sx72a tid Silicon Sculptor II Text: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case	Original	TM1019 RTSX32su Actel a54sx72a tid Silicon Sculptor II	PDF
RTSX72 Abstract: No abstract text available Text: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case	Original	TM1019 RTSX72	PDF
gearbox 405 Abstract: DS1024 FTN256 TN1137 resistor 330 Ohm DATA SHEET AEC-Q100 Text: LA-LatticeXP2 Family Data Sheet DS1024 Version 01.2, May 2009 LA-LatticeXP2 Family Data Sheet Introduction May 2009 Data Sheet DS1024 • Flexible I/O Buffer Features • sysIO buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II	Original	DS1024 DS1024 HSTL15 HSTL18 AEC-Q100 gearbox 405 FTN256 TN1137 resistor 330 Ohm DATA SHEET	PDF
Untitled Abstract: No abstract text available Text: LA-LatticeXP2 Family Data Sheet DS1024 Version 01.3, January 2012 LA-LatticeXP2 Family Data Sheet Introduction January 2012 Data Sheet DS1024 Features  Flexible I/O Buffer • sysIO buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II	Original	DS1024 DS1024 HSTL15 HSTL18 AEC-Q100	PDF
LAXP2-5E-5TN144E Abstract: DS1024 TN1137 AEC-Q100 turbo encoder simulink QNEG01 Text: LA-LatticeXP2 Family Data Sheet DS1024 Version 01.1, August 2008 LA-LatticeXP2 Family Data Sheet Introduction June 2008 Data Sheet DS1024 • Flexible I/O Buffer Features • sysIO buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II	Original	DS1024 DS1024 HSTL15 HSTL18 AEC-Q100 LAXP2-5E-5TN144E TN1137 turbo encoder simulink QNEG01	PDF
Untitled Abstract: No abstract text available Text: LA-LatticeXP2 Family Data Sheet DS1024 Version 01.2, May 2009 LA-LatticeXP2 Family Data Sheet Introduction May 2009 Data Sheet DS1024 Features Flexible I/O Buffer • sysIO buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II	Original	DS1024 DS1024 HSTL15 HSTL18 AEC-Q100	PDF
gigabyte 845 crb Abstract: msi G31 crb AB38R EA27 RAMB16 PPC405D5 A13-C12 Equivalence transistor bc 398 TRANSISTOR MARKING YB 826 RISCwatch Text: Virtex-II Pro Platform FPGA Documentation • • • • Advance Product Specification PPC405 User Manual PPC405 Processor Block Manual Rocket I/O™ Transceiver User Guide March 2002 Release R R The Xilinx logo shown above is a registered trademark of Xilinx, Inc.	Original	PPC405 XC2064, XC3090, XC4005, XC5210 TXBYPASS8B10B, gigabyte 845 crb msi G31 crb AB38R EA27 RAMB16 PPC405D5 A13-C12 Equivalence transistor bc 398 TRANSISTOR MARKING YB 826 RISCwatch	PDF
Untitled Abstract: No abstract text available Text: LatticeXP2 Family Data Sheet DS1009 Version 2.1, August 2014 LatticeXP2 Family Data Sheet Introduction February 2012 Data Sheet DS1009  Flexible I/O Buffer Features • sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II	Original	DS1009 DS1009 HSTL15 HSTL18	PDF
Untitled Abstract: No abstract text available Text: LatticeXP2 Family Data Sheet DS1009 Version 02.0, March 2014 LatticeXP2 Family Data Sheet Introduction February 2012 Data Sheet DS1009  Flexible I/O Buffer Features • sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II	Original	DS1009 DS1009 HSTL15 HSTL18	PDF

Untitled Abstract: No abstract text available Text: LatticeXP2 Family Data Sheet DS1009 Version 01.6, August 2008 LatticeXP2 Family Data Sheet Introduction February 2008 Data Sheet DS1009  Flexible I/O Buffer Features • sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II	Original	DS1009 DS1009 HSTL15 HSTL18 XP2-17	PDF
LFXP2-17E-5QN208C Abstract: FTN256 lfxp2-5e LFXP2-5E-5QN208C LFXP2-8E-6FTN256C lfxp2-8E LFXP2-30E-6FTN256C XP2 LFXP2-5E-5QN208C LFXP2-30E-5FTN256I LFXP2-5E-5FTN256C Text: LatticeXP2 Family Data Sheet DS1009 Version 01.6, August 2008 LatticeXP2 Family Data Sheet Introduction February 2008 Data Sheet DS1009 • Flexible I/O Buffer Features • sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II	Original	DS1009 DS1009 HSTL15 HSTL18 XP2-17 LFXP2-17E-5QN208C FTN256 lfxp2-5e LFXP2-5E-5QN208C LFXP2-8E-6FTN256C lfxp2-8E LFXP2-30E-6FTN256C XP2 LFXP2-5E-5QN208C LFXP2-30E-5FTN256I LFXP2-5E-5FTN256C	PDF
FTN256 Abstract: LFXP2-30E-5FTN256I LFXP2-8E-6FTN256C LFXP2-17E-5FTN256I LFXP2-8E-5FTN256C FTBGA 256 LFXP2-17E-6FT256I8W LFXP2-17E-7FTN256C LFXP2-5E-6TN144C LFXP2-5E-7FTN256C Text: LatticeXP2 Family Data Sheet DS1009 Version 01.4, April 2008 LatticeXP2 Family Data Sheet Introduction February 2008 Preliminary Data Sheet DS1009 • Flexible I/O Buffer Features • sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II	Original	DS1009 DS1009 HSTL15 HSTL18 FTN256 LFXP2-30E-5FTN256I LFXP2-8E-6FTN256C LFXP2-17E-5FTN256I LFXP2-8E-5FTN256C FTBGA 256 LFXP2-17E-6FT256I8W LFXP2-17E-7FTN256C LFXP2-5E-6TN144C LFXP2-5E-7FTN256C	PDF
FTBGA thermal resistance Abstract: LFXP2-8E LFXP2-5E-5TN144I FPGA LFXP2-17E-5FTN256I8W lfxp25e5tn144c LFXP2-5E-5TN144C Text: LatticeXP2 Family Data Sheet DS1009 Version 01.3, February 2008 LatticeXP2 Family Data Sheet Introduction February 2008 Preliminary Data Sheet DS1009 • Flexible I/O Buffer Features • sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II	Original	DS1009 DS1009 HSTL15 HSTL18 XP2-17 FTBGA thermal resistance LFXP2-8E LFXP2-5E-5TN144I FPGA LFXP2-17E-5FTN256I8W lfxp25e5tn144c LFXP2-5E-5TN144C	PDF
lfxp2 Abstract: TN1137 Text: LatticeXP2 Family Data Sheet DS1009 Version 01.8, January 2012 LatticeXP2 Family Data Sheet Introduction January 2012 Data Sheet DS1009  Flexible I/O Buffer Features • sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II	Original	DS1009 DS1009 HSTL15 HSTL18 XP2-17 lfxp2 TN1137	PDF
LFXP2-5E-5QN208C Abstract: lfxp25e5tn144c LFXP2-17E LFXP2-5E LFXP2-8E-7FTN256C 16X4 XP2-17 TN1126 FTBGA 256 16x4 ENCODER Text: LatticeXP2 Family Data Sheet DS1009 Version 01.6, August 2008 LatticeXP2 Family Data Sheet Introduction February 2008 Data Sheet DS1009  Flexible I/O Buffer Features • sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II	Original	DS1009 DS1009 HSTL15 HSTL18 XP2-17 LFXP2-5E-5QN208C lfxp25e5tn144c LFXP2-17E LFXP2-5E LFXP2-8E-7FTN256C 16X4 XP2-17 TN1126 FTBGA 256 16x4 ENCODER	PDF
LFXP2-17E-5QN208C Abstract: lfxp2-5e-5ftn256c lfxp2-5e-5tn144c LFXP2-8E-5FTN256I 16X4 XP2-17 LFXP2-40E LFXP2-5E-6TN144C sequential gearbox LFXP2-8E-5TN144I Text: LatticeXP2 Family Data Sheet DS1009 Version 01.7, April 2011 LatticeXP2 Family Data Sheet Introduction February 2008 Data Sheet DS1009  Flexible I/O Buffer Features • sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II	Original	DS1009 DS1009 HSTL15 HSTL18 128eristics XP2-17 LFXP2-17E-5QN208C lfxp2-5e-5ftn256c lfxp2-5e-5tn144c LFXP2-8E-5FTN256I 16X4 XP2-17 LFXP2-40E LFXP2-5E-6TN144C sequential gearbox LFXP2-8E-5TN144I	PDF
mip283 Abstract: P124d ST P239 p037 ke EL B17 A017 I-CUBE ior p135 p005 ab 48 tag 91 P106t TI Marking P272 Text: •Pt I - C u b IQX Family Data Sheet e m F eatures D e s c r ip t io n • SRAM-based, in-system programmable The IQX family of SRAM-based bit-oriented switching devices is • Switch Matrix manufactured using a 0.6nm CMOS process. These devices offer clock speeds of up to 133 MHz and pin-to-pin delay as low	OCR Scan		PDF
TI Marking P272 Abstract: p135L mip283 L5106 ALI 3101 C I-CUBE iq P109t transistor P239 416L CA3125 Text: •Pt I - C u b IQX Family Data Sheet e m F eatures D e s c r ip t io n • SRAM-based, in-system programmable The IQX family of SRAM-based bit-oriented switching devices is • Switch Matrix manufactured using a 0.6nm CMOS process. These devices offer clock speeds of up to 133 MHz and pin-to-pin delay as low	OCR Scan		PDF
Data Vision P135 Abstract: I-CUBE Dp028d data vision p113 p039 tms 9980 processor P112-P115 4J, P113 5 PIN ln 7805 RG 5 OASIS Text: I-Cube PSX Family Data Sheet Features Description SRAM-based, In-system Programmable Switch Matrix - Non-Blocking - Programmable Bus Widths of 4 ,8 ,1 6 and 32 bits - Identical and Predictable Delays - One-to-One, One-to-Many and Many-toOne Connections - RapidConnect parallel interface for	OCR Scan	2328-C D-11-013 Data Vision P135 I-CUBE Dp028d data vision p113 p039 tms 9980 processor P112-P115 4J, P113 5 PIN ln 7805 RG 5 OASIS	PDF

RS-232 JTAG MATRIX Search Results

RS-232 JTAG MATRIX Datasheets Context Search

GMM AM08

AMBA AXI verilog code

AMBA AXI to APB BUS Bridge vhdl code

RTSX32SU CQ84

RTSX32SU

RTSX32su

RTSX72

gearbox 405

Untitled

LAXP2-5E-5TN144E

Untitled

gigabyte 845 crb

Untitled

Untitled

Untitled

LFXP2-17E-5QN208C

FTN256

FTBGA thermal resistance

lfxp2

LFXP2-5E-5QN208C

LFXP2-17E-5QN208C

mip283

TI Marking P272

Data Vision P135