NT6861B
Abstract: 6502 timing diagram 256 x 8 bit SRAM
Text: NT6861B 8-Bit Microcontroller for Monitor Features Hardware sync signals polarity & freq. evaluator 2 Built-In I C bus interface Supporting VESA DDC1/2B function Six-interrupt sources - INTV Vsync INT - INTE (External INT with rising edge trigger) - INTMR (Timer INT )
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NT6861B
NT6861B
6502 timing diagram
256 x 8 bit SRAM
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Untitled
Abstract: No abstract text available
Text: KM23SV32205T Synch. MROM 1M x32 Synchronous MASKROM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Switchable organization 2,097,152 x 16 word mode / 1,048,576 x 32(double word mode) • All inputs are sampled at the rising edge of the system clock
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KM23SV32205T
33MHz
50MHz
66MHz
86TSOP2
KM23SV32205T
86-TSOP2-400)
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AR19
Abstract: KM23SV32205T-15 KM23SV32205T-20 KM23SV32205T-30 RA12
Text: KM23SV32205T Synch. MROM 1M x32 Synchronous MASKROM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Switchable organization 2,097,152 x 16 word mode / 1,048,576 x 32(double word mode) • All inputs are sampled at the rising edge of the system clock
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KM23SV32205T
33MHz
50MHz
66MHz
86TSOP2
AR19
KM23SV32205T-15
KM23SV32205T-20
KM23SV32205T-30
RA12
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7861C
Abstract: el7861c
Text: EL7861C EL7861C Rising Edge Delay Driver mRFOBMAKCE F e a tu r e s G e n e r a l D e s c r ip t io n • • • • • • • • T he EL7861 provides 1.0A of peak cu rren t for m any driver ap plications. T he rising edge of th e o u tp u t can be delayed up to
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EL7861C
EL7861
7861C
el7861c
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Untitled
Abstract: No abstract text available
Text: ADE-203-223 A (Z) * HM5283206 Series 131,072-word x 32-bit x 2-bank Synchronous Graphic RAM Preliminary HITACHI — Self refresh (1024 refresh cycles: 16 ms) All inputs and outputs signals refers to the rising edge of the clock input. The HM5283206 provides
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ADE-203-223
HM5283206
072-word
32-bit
HM5283206FP-10
HM5283206FP-12
HM5283206FP-15
100-pin
FP-100)
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Untitled
Abstract: No abstract text available
Text: LH5494 FEATURES • Fast Cycle Times: 30/35 ns Frequency: 33/28.5 MHz • Serial Data In; Parallel Data Out • Serial Output for Cascading Input Register • Two Read Enable Inputs and One Write Enable Input, Sampled on Rising Edge of the Appropriate Clock
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LH5494
LH5494
-----------------------------------32-pin
PLCC32-P-R450)
LH5494U-25
32-pin
5494M
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Untitled
Abstract: No abstract text available
Text: HM5216326 Serie 16M LVTTL interface SGRAM 2-Mword x 32-bit 125 MHz/100 MHz/83 MHz HITACHI ADE-203-678B (Z) Preliminary, Rev. 0.3 Jan. 14,1998 Description All inputs and outputs signals refers to the rising edge of the clock input. The HM5216326 provides 2
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HM5216326
32-bit)
Hz/100
Hz/83
ADE-203-678B
FP-100H
TFP-100H
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mvab
Abstract: ZW22 HM5241605 HM5241605TT-15 HM5241605TT-17 HM5241605TT-20
Text: ADE-203-186A Z HM5241605 Series 131,072-word x 16-bit x 2-bank Synchronous Dynamic RAM A ll inputs and outputs are referred to the rising edge o f the clock input. The HM5241605 is offered in 2 banks for improved performance. Features Ordering Information
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ADE-203-186A
HM5241605
072-word
16-bit
Hz/57
Hz/50
P////77K
///7//77//7/7X
mvab
ZW22
HM5241605TT-15
HM5241605TT-17
HM5241605TT-20
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Untitled
Abstract: No abstract text available
Text: HM5221605 Series Prelim inary 65,536-word x 16-bit x 2-bank Synchronous Dynamic RAM A ll inputs and outputs are referred to the rising edge o f the clock input. The HM5221605 is offered in 2 banks for improved performance. Features Ordering Information Type No.
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HM5221605
536-word
16-bit
HM5221605TT-20
HM5221605TT-17
HM522160517-15
400-mil
50-pin
TTP-50DA)
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74F74
Abstract: 74F74PC 74F74SC 74F74SJ M14A M14D MS-001 N14A
Text: Revised July 1999 E M IC D N D U C T D R T M 74F74 Dual D-Type Positive Edge-Triggered Flip-Flop th e outputs until th e next rising edge of the Clock Pulse input. G eneral Description T he F74 is a dual D -type flip-flofaw ith D irect C lear and Set inputs and com plem entary Q, Q outputs. Inform ation at
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74F74
74F74
74F74PC
74F74SC
74F74SJ
M14A
M14D
MS-001
N14A
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Untitled
Abstract: No abstract text available
Text: ADE-203-199 A (Z) HM5221605 Series 65,536-word x 16-bit x 2-bank Synchronous Dynamic RAM Preliminary Rev. 0.1 Sep. 22, 1994 HITACHI All inputs and outputs are referred to the rising edge of the clock input. The HM5221605 is offered in 2 banks for improved performance.
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ADE-203-199
HM5221605
536-word
16-bit
HM5221605TT-20
HM5221605TT-17
HM5221605TT-15
400-mil
50-pin
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Untitled
Abstract: No abstract text available
Text: HM5221605 Series Preliminary 65,536-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI A ll inputs and outputs are referred to the rising edge of the clo ck input. The HM5221605 is offered in 2 banks for improved performance. Features Rev. 0.1 Sep. 22,1994
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HM5221605
536-word
16-bit
HM5221605TT-20
HM5221605TT-17
HM5221605TT-15
400-mil
50-pin
TTP-50DA)
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Untitled
Abstract: No abstract text available
Text: HM5221605 Series 65,536-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI ADE-203-199B Z Rev. 2.0 Nov. 14, 1996 Description All inputs and outputs are referred to the rising edge of the clock input. The HM5221605 is offered in 2 banks for improved performance.
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HM5221605
536-word
16-bit
ADE-203-199B
Hz/58
Hz/66
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Untitled
Abstract: No abstract text available
Text: HM5221605 Series 65,536-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI ADE-203-199A Z Rev. 1.0 Jun. 22, 1995 Description All inputs and outputs are referred to the rising edge of the clock input. The HM5221605 is offered in 2 banks for improved performance.
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HM5221605
536-word
16-bit
ADE-203-199A
Hz/58
Hz/50
P7Z07
/77T7,
44TbED3
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Untitled
Abstract: No abstract text available
Text: HM5216165 Series 524,288-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI ADE-203-280A Z Rev. 1.0 Dec. 20, 1996 Description All inputs and outputs are referred to the rising edge of the clock input. The HM5216165 is offered in 2 banks for improved performance.
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HM5216165
288-word
16-bit
ADE-203-280A
Hz/83
Hz/66
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1A11BS
Abstract: No abstract text available
Text: ADE-203-304A Z HM5216805 Series HM5216405 Series 1,048,576-word x 8-bit x 2-bank Synchronous Dynamic RAM 2,097,152-word x 4-bit x 2-bank Synchronous Dynamic RAM HITACHI AH inputs and outputs are referred to the rising edge of the clock input. The HM521680S Series,
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ADE-203-304A
HM5216805
HM5216405
576-word
152-word
HM521680S
HM5216805TT-10
HM5216805TT-12
HM5216805TT-15
HM5216405TT-10
1A11BS
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Untitled
Abstract: No abstract text available
Text: ADE-203-186A Z HM5241605 Series 131,072-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI A ll inputs and outputs are referred to the rising No, S Ordering Information edge o f the clock input. The HM5241605 is offered in 2 banks for improved performance.
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ADE-203-186A
HM5241605
072-word
16-bit
400-mil
50-pin
TTP-50D)
HM5241605TT-20
HM5241605TT-17
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Untitled
Abstract: No abstract text available
Text: Semiconductor DS90CR217/DS90CR218 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 75 MHz Features • 20 to 75 MHz sh ift clock support This chipset is an ideal m eans to solve EMI and cable size problem s associated with w ide, high speed T T L interfaces.
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DS90CR217/DS90CR218
21-Bit
Usi0-272-9959
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Untitled
Abstract: No abstract text available
Text: HM5216326 Series 16M LVTTL interface SGRAM 2-Mword x 32-bit 125 MHz/100 MHz/83 MHz HITACHI ADE-203-678B (Z) Preliminary, Rev. 0.3 Jan. 14, 1998 Description All inputs and outputs signals refers to the rising edge of the clock input. The HM 5216326 provides 2
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HM5216326
32-bit)
Hz/100
Hz/83
ADE-203-678B
z/100
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mhtl
Abstract: No abstract text available
Text: HM5221605 Series 65,536-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI ADE-203-199A Z Rev. 1.0 Jun. 22,1995 Description All inputs and outputs are referred to the rising edge of the clock input. The HM 5221605 is offered in 2 banks for improved performance.
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HM5221605
536-word
16-bit
ADE-203-199A
Hz/58
Hz/50
\z//////////////77x\
/777777T
mhtl
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Untitled
Abstract: No abstract text available
Text: ju*1989 DM54LS461 /DM74LS461 Octal Counter General Description The LS461 is an 8 -bit synchronous counter with parallel load, dear, and hold capability. Two function select inputs lo, h provide one of four operations which occur synchro nously on the rising edge of the do ck (CK).
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DM54LS461
/DM74LS461
LS461
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Untitled
Abstract: No abstract text available
Text: HM5216165 Series 524,288-word x 16-bit x 2-bank Synchronous Dynamic RA M HITACHI ADE-203-280 A (Z) Preliminary Rev. 0.1 Oct. 20,1995 Description A ll inputs and outputs are referred to the rising edge of the clock input. The HM5216165 is offered in 2 banks for improved performance.
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HM5216165
288-word
16-bit
ADE-203-280
Hz/83
Hz/66
GG27bb2
HM5216165TT
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NIPPON SMG
Abstract: 5216805 gt77
Text: HM5216405 Series Preliminary 2,097,152-word x 4-bit x 2-bank Synchronous Dynamic RAM HITACHI All Inputs and outputs are referred to the rising edge of the clock input. The HM5216405 is offered In 2 banks for improved performance. Features R b v . 0.1 Apr. 5 ,1 9 9 5
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HM5216405
152-word
HM5216405TT-10
HM5216405TT-12
HM521640STT-15
400-mll
44-pln
TTP-44DE)
Hz/83
NIPPON SMG
5216805
gt77
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Untitled
Abstract: No abstract text available
Text: HM5216165 Series 524,288-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI ADE-203-280 A (Z) Preliminary Rev. 0.1 Oct. 20, 1995 Description All inputs and outputs are referred to the rising edge of the clock input. The HM5216165 is offered in 2 banks for improved performance.
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HM5216165
288-word
16-bit
ADE-203-280
Hz/83
Hz/66
5216165TT
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