pj 69 SMD diode
Abstract: RX-2B RX2C RX2b bs3-1000 Monitor VD58 smd diode pj 72 c8051f320-gq VD58 ISL54100
Text: ISL54100AHDMI-EVALZ, ISL54105ACRZ-EVALZ Operation Manual for Intersil’s 4:1 and 1:1 TMDS HDMI Regenerator Evaluation Kits Application Note April 1, 2009 AN1453.2 Thank you for requesting Intersil’s high-performance TMDS signal multiplexor/regenerator/retimer evaluation kit. This
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ISL54100AHDMI-EVALZ,
ISL54105ACRZ-EVALZ
AN1453
ISL5410xA
pj 69 SMD diode
RX-2B
RX2C
RX2b
bs3-1000
Monitor VD58
smd diode pj 72
c8051f320-gq
VD58
ISL54100
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dell 2000fp
Abstract: tmds receiver dell monitor circuit diagram DVI dual link receiver 2000FP capture HDMI video IC monitor Dell 2000fp projector dell ISL54105A ISL54105ACRZ
Text: ISL54105A Key Features Data Sheet June 4, 2008 FN6716.0 TMDS Regenerator Features The ISL54105A is a high-performance TMDS timing regenerator containing a programmable equalizer and a clock data recovery CDR function for each of the 3 TMDS pairs in an HDMI or DVI signal. The TMDS data outputs of
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ISL54105A
FN6716
ISL54105A
JESD-MO220.
dell 2000fp
tmds receiver
dell monitor circuit diagram
DVI dual link receiver
2000FP
capture HDMI video IC
monitor Dell 2000fp
projector dell
ISL54105ACRZ
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dell monitor circuit diagram
Abstract: dell 2000fp DELL power supply diagram TMDS PCB design guidelines DVI dual link receiver monitor Dell 2000fp tmds receiver Chroma ISL54105 ISL54105CRZ
Text: ISL54105 Key Features Data Sheet June 11, 2008 FN6723.0 TMDS Regenerator Features The ISL54105 is a high-performance TMDS timing regenerator containing a programmable equalizer and a clock data recovery CDR function for each of the 3 TMDS pairs in an HDMI or DVI signal. The TMDS data outputs of
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ISL54105
FN6723
ISL54105
JESD-MO220.
dell monitor circuit diagram
dell 2000fp
DELL power supply diagram
TMDS PCB design guidelines
DVI dual link receiver
monitor Dell 2000fp
tmds receiver
Chroma
ISL54105CRZ
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dell monitor circuit diagram
Abstract: DVI TMDS PCB design guidelines dell 2000fp monitor Dell 2000fp ISL54105 ISL54105A ISL54105CRZ TB379 DVI RECEIVER PCB design guidelines
Text: ISL54105 Key Features S DESIGN W E N R O NDED F COMME E ISL54105A E R T O N Data Sheet SEE T H June 11, 2008 FN6723.0 TMDS Regenerator Features The ISL54105 is a high-performance TMDS timing regenerator containing a programmable equalizer and a clock data recovery CDR function for each of the 3 TMDS
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ISL54105
FN6723
ISL54105
JESD-MO220.
dell monitor circuit diagram
DVI TMDS PCB design guidelines
dell 2000fp
monitor Dell 2000fp
ISL54105A
ISL54105CRZ
TB379
DVI RECEIVER PCB design guidelines
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ABBA
Abstract: LXT6051QE 9922H AU-AIS LXT6051 VC12 SLXT6051 LXT6251 W117
Text: Datasheet JUNE 1999 Revision 2.0 LXT6051 STM-1/0 SDH Overhead Terminator General Description Features The LXT6051 Overhead Terminator implements the Regenerator Section Termination, Multiplexer Section Termination and Higher Order Path Termination in STM-0
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LXT6051
LXT6051
51Mb/s)
155Mb/s)
LXT6251
ABBA
LXT6051QE
9922H
AU-AIS
VC12
SLXT6051
LXT6251
W117
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9718h
Abstract: 11973H VC12 LEVEL ONE COMMUNICATIONS SXT6051 SXT framer HT 648 Decoder Rx 9802h
Text: DATA SHEET MAY 1998 Revision 1.1 SXT6051 STM-1/0 SDH Overhead Terminator General Description Features The SXT6051 Overhead Terminator implements the Regenerator Section Termination, Multiplexer Section Termination and Higher Order Path Termination in STM-0
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SXT6051
SXT6051
51Mb/s)
155mB/s)
SXT6251
9718h
11973H
VC12
LEVEL ONE COMMUNICATIONS
SXT framer
HT 648 Decoder Rx
9802h
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all ic data
Abstract: decibel meter regenerator in optical MAX3676 MAX3676EHJ MAX3664
Text: 19-1537; Rev 1; 4/00 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier _Features ♦ Single +3.3V or +5.0V Power Supply ♦ Exceeds ITU/Bellcore SDH/SONET Regenerator Specifications ♦ Low Power: 237mW at +3.3V
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622Mbps,
237mW
MAX3676EHJ
MAX3676E/D
MAX3676
all ic data
decibel meter
regenerator in optical
MAX3676
MAX3676EHJ
MAX3664
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all ic data
Abstract: ANA 608 regenerator in optical MAX3664 MAX3676 MAX3676EHJ Fiber Optic regenerator 28
Text: 19-1537; Rev 0; 7/99 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier _Features ♦ Single +3.3V or +5.0V Power Supply ♦ Exceeds ITU/Bellcore SDH/SONET Regenerator Specifications ♦ Low Power: 237mW at +3.3V
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622Mbps,
237mW
MAX3676EHJ
MAX3676E/D
MAX3676
all ic data
ANA 608
regenerator in optical
MAX3664
MAX3676
MAX3676EHJ
Fiber Optic regenerator 28
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Untitled
Abstract: No abstract text available
Text: 19-1537; Rev 1; 4/01 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier _Features ♦ Single +3.3V or +5.0V Power Supply ♦ Exceeds ITU/Bellcore SDH/SONET Regenerator Specifications ♦ Low Power: 237mW at +3.3V
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622Mbps,
MAX3676
622Mbps
OC12/STM-4
MAX3676
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AN42
Abstract: Si5310 Si5310-BM pitch DD2200
Text: Si5310 P RECISION C LOCK M ULTIPLIER /R EGENERATOR IC Features Complete precision clock multiplier and clock regenerator device: ! Performs clock multiplication to one ! of two frequency ranges: 150–167 MHz or 600–668 MHz ! ! Jitter generation as low as
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Si5310
Si5310-BM
AN42
Si5310
pitch
DD2200
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AU-AIS
Abstract: Digital Alarm Clock by using ttl LXT e2 LXT6251A marking cod A2 regenerator in optical D4D12 LXT6051 LXT6051QE SSI 7200
Text: LXT6051 STM-1/0 SDH Overhead Terminator Datasheet The LXT6051 Overhead Terminator implements the Regenerator Section Termination, Multiplexer Section Termination and Higher Order Path Termination in STM-0 51Mb/s and STM-1 (155Mb/s) multiplexers. It provides micro-controller access for performance monitoring,
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LXT6051
LXT6051
51Mb/s)
155Mb/s)
LXT6251A
AU-AIS
Digital Alarm Clock by using ttl
LXT e2
LXT6251A
marking cod A2
regenerator in optical
D4D12
LXT6051QE
SSI 7200
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1084-18
Abstract: Internal diagram of ic 7495 regenerator LG1600KXH LG1600KXH0622 LG1600KXH2488 LG1605DXB TF1004A LG1600KXH4977 wolaver
Text: Data Sheet June 1999 LG1600KXH Clock and Data Regenerator Features • Integrated clock recovery and data retiming ■ Surface-mount package ■ Single ECL supply ■ Robust FPLL design ■ Operation up to BER = 1e–3 ■ SONET/SDH compatible loss of signal alarm
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LG1600KXH
OC-12
OC-96/STM-4
STM-32
DS99-255HSPL
1084-18
Internal diagram of ic 7495
regenerator
LG1600KXH0622
LG1600KXH2488
LG1605DXB
TF1004A
LG1600KXH4977
wolaver
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MAX3866
Abstract: MAX3875 MAX3875EHJ MAX3885
Text: 19-4789; Rev 0; 10/98 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC Features ♦ Exceeds ANSI, ITU, and Bellcore SONET/SDH Regenerator Specifications This device operates from a single +3.3V to +5.0V supply over a -40°C to +85°C temperature range. The typical
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400mW
32-pin
003UIRMS
803mm)
MAX3875
MAX3866
MAX3875
MAX3875EHJ
MAX3885
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SDI SERIALIZER
Abstract: all ic data MAX3831 MAX3866 MAX3876 MAX3876EHJ fz 85
Text: 19-1631; Rev 0; 1/00 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC Features ♦ Exceeds ANSI, ITU, and Bellcore SONET/SDH Regenerator Specifications This device operates from a +3.3V or +5.0V single supply over a -40°C to +85°C temperature range. Power
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445mW
MAX3876
32-pin
440mW
MAX3876
SDI SERIALIZER
all ic data
MAX3831
MAX3866
MAX3876EHJ
fz 85
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Untitled
Abstract: No abstract text available
Text: Product Overvic FEBRUARY 1998 Revision 7.0 SXT6051 STM-1/0 SDH Overhead Terminator General Description Features The SXT6051 Overhead Terminator implements the Regenerator Section Termination, Multiplexer Section Termination and Higher Order Path Termination in STM-0
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SXT6051
SXT6051
51Mb/s)
155Mb/s)
SXT6251
S4bT23b
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asahi glass delay line
Abstract: M51397AP M51395 SG314 AV20-22 ST T4 3560 M51395AP transformer 400Hz 115v 30P4 115v 400Hz circuit diagram
Text: MITSUBISHI ICs TV M51397AP SECAM CHROMA SYSTEM DESCRIPTION PIN CONFIGURATION IEW) The M51397AP is a semiconductor integrated circuit for SECAM system color television receivers. It CONTAINS chroma processor, chroma demodulator, DC regenerator and system switches for PAL/SECAM dual system.
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M51397AP
M51397AP
M51395AP
433619MHz.
M51395AP)
asahi glass delay line
M51395
SG314
AV20-22
ST T4 3560
M51395AP
transformer 400Hz 115v
30P4
115v 400Hz circuit diagram
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Untitled
Abstract: No abstract text available
Text: Datasheet JUNE 1999 Revision 2.0 LXT6051 STM-170 SDH Overhead Terminator General Description The LXT6051 Overhead Terminator implements the Regenerator Section Termination, Multiplexer Section Termination and Higher Order Path Termination in STM-0 51Mb/s and STM-1 (155Mb/s) multiplexers. It provides
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LXT6051
STM-170
LXT6051
51Mb/s)
155Mb/s)
LXT6251
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Untitled
Abstract: No abstract text available
Text: HA11417 Color TV Chroma Processor/Demodulator • FUNCTIONS • • • • Chroma Amp. Subcarrier Regenerator Color Demodulator Flesh Correction ■ FEATURES • • • • • • Color difference matrix D C tint control Three low-output-impedance drivers for direct coupling
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HA11417
273mVp-p
845Hz
245Hz.
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C3262
Abstract: No abstract text available
Text: ANALOG DEVICES Fiber CjbticFfecausr withQjartizer and Clock FfeccveryandDataFtetirring Æ 0O 6 FEATURES M eets CCITT G.958 Requirements for S TM -4 Regenerator— Type A M eets Bellcore TR-NWT-000253 Requirements for OC-12 O utput Jitter: 2.5 Degrees RMS 622 Mbps Clock Recovery and Data Retiming
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16-Lead
R-16A)
C3262-8-1/98
C3262
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RY 227
Abstract: chroma section function HA11417 L-11
Text: HA11417 Color TV Chroma Processor/Demodulator • FU NCTIO N S • • • • Chroma Amp. Subcarrier Regenerator Color Demodulator Flesh Correction ■ FE A TU R E S • • • • • • Color difference matrix DC tint control Three low-output-impedance drivers for direct coupling
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HA11417
111-50pF
579545MHÃ
390pF2t
i82pF
400mVp-p
RY 227
chroma section function
HA11417
L-11
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Untitled
Abstract: No abstract text available
Text: w GEC PLESSEY PRELIMINARY INFORMATION S E M I C O N D U C T O R S DS3109 2 2 MV1445 COMBINED PCM HDB3 DECODER, DIGITAL CLOCK REGENERATOR AND TIMESLOT ZERO RECEIVER The MV1445 com bines the HDB3 Decoder, Digital Clock Regnerator and Tim eslot Zero Receiver functions required by
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DS3109
MV1445
MV1445
048Mbit
37bfl522
0D2043S
V1445/IG/DGAS
V1445/IG
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Untitled
Abstract: No abstract text available
Text: ANALO G D E V IC E S Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming AD807 FEATURES Meets CCITT G.958 Requirements for STM-1 Regenerator—Type A Meets Bellcore TR-NWT-000253 Requirements for OC-3 Output Jitter: 2.0 Degrees RMS 155 Mbps Clock Recovery and Data Retiming
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AD807
TR-NWT-000253
16-Pin
AD807
16-Lead
R-16A)
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Untitled
Abstract: No abstract text available
Text: Data Sheet June 1999 m ic r o e le c t r o n ic s group Lucent Technologies Bell Labs Innovations LG1600KXH Clock and Data Regenerator Features • Integrated clock recovery and data retiming ■ Surface-mount package ■ Single ECL supply ■ Robust FPLL design
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LG1600KXH
OC-12
OC-96/STM-4
STM-32
TF1004A
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807155
Abstract: a3607 1A227 EPITAXX erm
Text: AN ALO G D E V IC E S Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming A3607 FEATURES M eets CCITT G.958 Requirements for STM-1 Regenerator—Type A M eets Bellcore TR-NW T-000253 Requirem ents for OC-3 O utput Jitter: 2.0 Degrees RMS
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A3607
C2044a-2-3/97
AD807
807155
a3607
1A227
EPITAXX erm
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