QL3025-1PQ208C
Abstract: PQ208 QL3025 QL3025-1PB256C QL3025-1PF144C
Text: QL3025 / QL3025R 25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density PRELIMINARY DATA February, 1998 2 … 25,000 usable PLD gates, 204 I/O pins 16,128 bit RAM Option High Performance and High Density -25,000 Usable PLD Gates with 204 I/Os
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QL3025
QL3025R
-16-bit
QL3025-1PQ208C
PQ208
QL3025-1PB256C
QL3025-1PF144C
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Untitled
Abstract: No abstract text available
Text: QL3025 / QL3025R 25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density PRELIMINARY DATA March, 1998 2 … 25,000 usable PLD gates, 204 I/O pins 16,128 bit RAM Option High Performance and High Density -25,000 Usable PLD Gates with 204 I/Os
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QL3025
QL3025R
-16-bit
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intel 4040
Abstract: QL3004 transistor equivalent table 557 cmos 4040 datasheet general cross references QL5064 QL4009 QL4016 QL4058 QL5030
Text: EMBEDDED STANDARD PRODUCT A GENERATION AHEAD ! The Vialink Antifuse in 0.35µ µm CMOS QuickLogic Corporation 1277 Orleans Dr. Sunnyvale, CA 94089-1138 General Information: Applications Hotline FAX: EMAIL: WEB SITE: 408 990-4000 (408) 990-4100 (408) 990-4040
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cpu Intel 4040
Abstract: intel 4040 3com 226 QAN19 Modulating Direct Digital Synthesizer in a QuickLogic FPGA QL3025 pASIC 1 Family 4040 cmos 4040 intel cmos 4040 datasheet
Text: LEADING THE REVOLUTION IN FPGAs The Vialink Antifuse in 0.35µm CMOS QuickLogic Corporation 1277 Orleans Dr. Sunnyvale, CA 94089-1138 General Information: Applications Hotline FAX: EMAIL: WEB SITE: 408 990-4000 (408) 990-4100 (408) 990-4040 info@quicklogic.com
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NC-T3
Abstract: PF144 PQ208 QL3025 QL3025-1PB256C QL3025-1PF144C QL3025-1PQ208C IOG20 jtag pinout
Text: QL3025 25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density April, 1999 4 pASIC 3 HIGHLIGHTS … 25,000 usable PLD gates, 204 I/O pins High Performance and High Density -25,000 Usable PLD Gates with 204 I/Os -16-bit counter speeds over 300 MHz, data path speeds over 400 MHz
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QL3025
-16-bit
QL3025-rev.
NC-T3
PF144
PQ208
QL3025
QL3025-1PB256C
QL3025-1PF144C
QL3025-1PQ208C
IOG20
jtag pinout
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Untitled
Abstract: No abstract text available
Text: QL3025 / QL3025R 25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density PRELIMINARY DATA . 25,000 usable PLD gates, 204 I/O pins 16,128 bit RAM Option S High Performance and High Density -25,000 Usable PLD Gates with 204 I/Os -16-bit counter speeds over 250 MHz, data path speeds over 275 MHz
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OCR Scan
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PDF
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QL3025
QL3025R
-16-bit
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Untitled
Abstract: No abstract text available
Text: QL3025 25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density April, 1999 pASIC 3 HIGHLIGHTS . 25,000 usable PLD gates, 204 I/O pins S High Performance and High Density -25,000 Usable PLD Gates with 204 I/Os -16-bit counter speeds over 300 MHz, data path speeds over 4 0 0 MHz
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OCR Scan
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PDF
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QL3025
-16-bit
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