PI74
Abstract: PI74SSTU32866 Q13A SN74SSTU32866 SSTU32866
Text: PI74SSTU32866 25-bit 1:1 or 14-bit 1:2 Configurable Registered Buffer with Parity Product Features Product Description • PI74 SSTU32866 is designed for low-voltage operation, VDD = 1.8V • Supports Low Power Standby Operation • All Inputs are SSTL_18 Compatible, except RST, C0, C1,
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PDF
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PI74SSTU32866
25-bit
14-bit
SSTU32866
PS8739
PI74
PI74SSTU32866
Q13A
SN74SSTU32866
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87391
Abstract: No abstract text available
Text: FEATURES AND SPECIFICATIONS Features and Benefits • Fully shielded for maximum EMI/RFI protection ■ Available in 2 styles: fork lock for additional PCB retention and fitting nail for true SMT ■ Dual-cantilever contact design for repeated cycling ■ Preloaded SMT leads help insure coplanarity
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PDF
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PS-87391
87391
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MXF95001
Abstract: MXF 95001
Text: hole% Mini-DIN :EATURES AND SPECIFICATJONS atures and Benefits Fully shielded for maximum EMI/RN protection Available in 2 styles: fork lock for additional PCB retention and fitting nail for true SMT Dual-cantilever contact design for repeated cycling Preloaded SMT leads help insure coplanarity
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Original
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PDF
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Ps-87391
PS-95001
901rm
271rm
MXF95001
MXF 95001
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Untitled
Abstract: No abstract text available
Text: PI74SSTU32866 25-bit 1:1 or 14-bit 1:2 Configurable Registered Buffer with Parity Product Features Product Description • PI74SSTU32866 is a low-voltage device with VDD = 1.8V • Supports Low Power Standby Operation • All Inputs are SSTL_18 Compatible, except RST, C0, C1,
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Original
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PDF
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PI74SSTU32866
25-bit
14-bit
PI74SSTU32866
DDR2-533/400
PS8739A
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D8-D25
Abstract: PI74SSTU32866 Q13A
Text: PI74SSTU32866 25-bit 1:1 or 14-bit 1:2 Configurable Registered Buffer with Parity Product Features Product Description • PI74SSTU32866 is a low-voltage device with VDD = 1.8V • Supports Low Power Standby Operation • All Inputs are SSTL_18 Compatible, except RST, C0, C1,
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Original
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PDF
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PI74SSTU32866
25-bit
14-bit
PI74SSTU32866
96-Ball
DDR2-533/400
PS8739B
D8-D25
Q13A
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MiniDIN 8
Abstract: i002 MINI-DIN RECEPTACLE
Text: 10 P L A T IN G OPTION P A R T NO. T IN / L E A D 87391-1801 TIN 87391-4801 1 POSITION OF SOLDER LEADS SHALL NOT BE GREATER THAN O.IO/ .004 ABOVE OR 0 .0 5 /(.002) BELOW THE SEATING PLANE (DATUM C). 2 CO-PLANARITY OF SOLDER LEADS SHALL BE WITHIN 0 J0/(.00 4).
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OCR Scan
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PDF
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PS-87391
03BOLS
SD-87391-1801
MiniDIN 8
i002
MINI-DIN RECEPTACLE
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