PMC-971147
Abstract: POS-PHY ATM format
Text: COMPATIBILITY SPECIFICATION PMC-Sierra, Inc. POS-PHY Level 2 PMC-971147, ISSUE 5 SATURN-COMPATIBLE INTERFACE FOR POS PHY DEVICES POS-PHY™ SATURN COMPATIBLE
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PMC-971147,
PMC-971147
POS-PHY ATM format
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PMC-1980495
Abstract: STM-16 STS-48 TSX 017
Text: PMC-Sierra, Inc. COMPATIBILITY SPECIFICATION POS-PHY Level 3 PMC-1980495, ISSUE 4 SATURN-COMPATIBLE INTERFACE FOR POS PHY DEVICES POS-PHY™ Level 3 SATURN COMPATIBLE
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PMC-1980495,
PMC-1980495
STM-16
STS-48
TSX 017
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AF200
Abstract: MAC layer sequence number MB250
Text: POS-PHY Level 4 MegaCore Function POSPHY4 August 2001; ver. 1.00 Data Sheet Introduction Optimized for the Altera APEXTM II device architecture, the POS-PHY level 4 MegaCore® function (POSPHY4) interfaces cell and packet transfers between physical (PHY) and link layer devices. The POSPHY4
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OC-192,
AF200
MAC layer sequence number
MB250
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PMC-1991635
Abstract: saturn ups OC192 hdlc framing
Text: POS-PHY LEVEL 4 INTERFACE SPECIFICATION PMC-1991635 ISSUE 6 SATURN 10 GIGABIT PACKET/CELL PHY INTERFACE POS-PHYTM LEVEL 4 A SATURN PACKET AND CELL INTERFACE SPECIFICATION FOR OC192 SONET/SDH AND 10 GIGABIT ETHERNET ISSUE 6: FEBRUARY 2001 PMC-Sierra, Inc. Page 1
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PMC-1991635
OC192
PMC-1991635
saturn ups
hdlc framing
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altera marking Code Formats Cyclone 2
Abstract: verilog code for spi4.2 to fifo vhdl 4-bit binary calculator cyclone FPGA 144 EP3C40F780C6 EP4SGX230DF29C3ES EP4SGX70 PM3388 EP3SE50F780 OIF-SPI4-02
Text: POS-PHY Level 4 MegaCore Function User Guide POS-PHY Level 4 MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-IPPOSPHY4-10.0 Document last updated for Altera Complete Design Suite version: Document publication date: 10.0
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UG-IPPOSPHY4-10
altera marking Code Formats Cyclone 2
verilog code for spi4.2 to fifo
vhdl 4-bit binary calculator
cyclone FPGA 144
EP3C40F780C6
EP4SGX230DF29C3ES
EP4SGX70
PM3388
EP3SE50F780
OIF-SPI4-02
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fifo vhdl
Abstract: POS-PHY pmc OC48 PM5351 PM7325 ep1m20 vhdl code for phy interface
Text: POS-PHY Level 2 & 3 Compiler MegaCore Functions April 2001 User Guide v0.5.0 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com A-UG-POS-PHY_COMP-0.5.0 POS-PHY Level 2 & 3 Compiler MegaCore Functions User Guide Altera, ACEX, APEX, APEX 20K, MegaCore, MegaWizard, Mercury, OpenCore, Quartus and Quartus II are trademarks and/or
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8B10B
Abstract: 8B10B in serial communication
Text: µPD98441, µPD98442 eTR Utopia/POS-PHY to LVDS Interface Product Letter Description Express Transmitter Receiver for short: eTR is a powerful transceiver chip family designed to deliver reliable full-duplex high-speed point-to-point UTOPIA/POS-PHY data transfer over a serial LVDS link, either via the
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PD98441,
PD98442
PD98441)
S16608EE3V0PL00
8B10B
8B10B in serial communication
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AN166
Abstract: AN202 fpga frame buffer vhdl examples FIFO buffer threshold YDAT sonet testbench
Text: POS-PHY Level 4 MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com Core Version: Document Version: Document Date: 1.0.0p4 1.0.0p4 August 2002 Copyright POS-PHY Level 4 MegaCore Function User Guide Copyright 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo,
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700Mb/s
AN166,
AN120
OIF2000
AN166
AN202
fpga frame buffer vhdl examples
FIFO buffer threshold
YDAT
sonet testbench
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PM3393
Abstract: XAUI
Text: Advance PM3393 S/UNI 1x10GE-XP Single Chip 10 Gigabit Ethernet LAN PHY For XAUI-Based Optics GENERAL DESCRIPTION • The S/UNI®-1x10GE-XP is a highly integrated single chip 10 Gigabit Ethernet LAN PHY supporting XAUIbased optical modules. The S/UNI 1x10GE-XP provides a POS-PHY
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PM3393
1x10GE-XP
-1x10GE-XP
1x10GE-XP
16-bit
OC-192
POS/10
PMC-2012355
PM3393
XAUI
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Gigabit Ethernet PHY
Abstract: PM3386 PM5358 PM5381 PM5382 PM7390
Text: PM3386 S/UNI -2xGE Dual Gigabit Ethernet Controller PMC-1991223 R4 • Standard OC-48 bandwidth Packet/Cell interface. • Compatible with PMC-Sierra devices supporting POS-PHY Level 3, including: • PM5381 S/UNI®-2488 ATM and POS physical layer device.
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PM3386
PMC-1991223
OC-48
PM5381
PM5358
-4x622
OC-48c
PM7390
S/UNI-MACH-48
PM5382
Gigabit Ethernet PHY
PM3386
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Untitled
Abstract: No abstract text available
Text: POS-PHY Level-3 PHY Layer Core March 29, 2002 Product Specification LogiCORE Facts Core Specifics Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: logicore@xilinx.com URL: www.xilinx.com/ipcenter Support: www.support.xilinx.com
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GR-253-CORE
Abstract: PM5358 PM5382
Text: PM5380 S/UNI 8x155 Released 8-Channel OC-3c ATM and POS Physical Layer Device FEATURES DEVICE INTERNETWORKING Other PMC-Sierra devices that implement the POS-PHY Level 3 interface include: • S/UNI 12xJET • S/UNI 4x622 • S/UNI 2488 • S/UNI 2xGE • S/UNI MACH48
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PM5380
8x155
12xJET
4x622
MACH48
16x155
PMC-2021288
GR-253-CORE
PM5358
PM5382
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XAPP623
Abstract: No abstract text available
Text: POS-PHY Level-4 Core v5.0 DS209 August 7, 2002 Product Specification LogiCORE Facts Features • Fully compliant with OIF-SPI4-02.0 System Packet Interface Level-4 SPI-4 Phase 2 standard • Supports POS, ATM, and Ethernet 10 Gbps applications • Delivered through CORE Generator providing easy
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DS209
OIF-SPI4-02
XAPP623
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GR-253-CORE
Abstract: PM5358 PM5379 PM5382 "network interface cards"
Text: PM5379 S/UNI 4x155 Release 4-Channel OC-3c ATM and POS Physical Layer Device FEATURES • Provides UTOPIA Level 3 compatible 32-bit wide System Interface clocked up to 104 MHz with parity support for ATM applications. • Provides SATURN POS-PHY Level 3 32-bit System Interface
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PM5379
4x155
32-bit
PM5380
8x155,
PM5382
16x155,
PM5358
4x622.
GR-253-CORE
PM5358
PM5379
"network interface cards"
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GR-253-CORE
Abstract: PM5358 PM5382 "network interface cards"
Text: PM5358 S/UNI 4x622 Released Quad Channel OC-12c ATM and POS Physical Layer Device FEATURES • Provides UTOPIA Level 3 32-bit wide System Interface clocked up to 104 MHz with parity support for ATM applications. • Provides SATURN® POS-PHY Level 3 32-bit System Interface
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PM5358
4x622
OC-12c
32-bit
PMC-2000331
GR-253-CORE
PM5358
PM5382
"network interface cards"
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1F2e
Abstract: DPS module
Text: POS-PHY Level 4 Interface Core V3.0 Product Specification August 31, 2001 LogiCORE Facts Core Specifics Supported Family Performance Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 URL: www.xilinx.com/support/techsup/appinfo
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OIF-SPI4-02
OC-192
1F2e
DPS module
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Untitled
Abstract: No abstract text available
Text: PHAST -12P Device STM-4/OC-12 SDH/SONET Overhead Terminator with CDB/PPP UTOPIA/POS-PHY Interface TXC-06412 DATA SHEET PRODUCT PREVIEW Line/Path Ring Ports LINE SIDE APPLICATIONS • SDH/SONET add/drop and terminal multiplexers • Linear MS/Line protection
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PHASTTM-12P
STM-4/OC-12
TXC-06412
VC-4-Xc/STS-1/STS-3c/STC-6c/STS9c/STS-12c
16-bit
TXC-06412-MB
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asynchronous fifo vhdl
Abstract: No abstract text available
Text: POS-PHY Level-3 Link Layer Core V1.0 March 29, 2002 Product Specification LogiCORE Facts Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: logicore@xilinx.com URL: www.xilinx.com/ipcenter Support: www.support.xilinx.com
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sml16
asynchronous fifo vhdl
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asynchronous fifo vhdl xilinx
Abstract: xilinx silicon device
Text: POS-PHY Level-3 Link Layer Core V2.01 March 29, 2002 Product Specification LogiCORE Facts TM Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: logicore@xilinx.com URL: www.xilinx.com/ipcenter Support: www.support.xilinx.com
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OIF-SPI3-01
OC-48
asynchronous fifo vhdl xilinx
xilinx silicon device
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g803
Abstract: No abstract text available
Text: PHAST-12P Device STM-4/OC-12 SDH/SONET Overhead Terminator with CDB/PPP UTOPIA/POS-PHY Interface TXC-06412B DATA SHEET PRELIMINARY TXC-06412B-MB, Ed. 3 December 2006 FEATURES • Bit-serial LVPECL SDH/SONET line interface with integrated clock recovery and
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PHAST-12P
STM-4/OC-12
TXC-06412B
TXC-06412B-MB,
VC-4-Xc/STS-1/STS3c/STC-6c/STS-9c/STS-12c
g803
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mpa08
Abstract: 178 09T AU-AIS PMC-971147 GR-253-CORE MPC8260 MPC860 TXC-06412 DSLAM structure MPD13
Text: PHAST -12P Device STM-4/OC-12 SDH/SONET Overhead Terminator with CDB/PPP UTOPIA/POS-PHY Interface TXC-06412 DATA SHEET PRODUCT PREVIEW Line/Path Ring Ports LINE SIDE APPLICATIONS • SDH/SONET add/drop and terminal multiplexers • Linear MS/Line protection
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STM-4/OC-12
TXC-06412
PHAST-12P
TXC-06412-MB,
mpa08
178 09T
AU-AIS
PMC-971147
GR-253-CORE
MPC8260
MPC860
TXC-06412
DSLAM structure
MPD13
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Untitled
Abstract: No abstract text available
Text: PHAST -12P Device STM-4/OC-12 SDH/SONET Overhead Terminator with CDB/PPP UTOPIA/POS-PHY Interface TXC-06412 DATA SHEET PRODUCT PREVIEW Line/Path Ring Ports LINE SIDE APPLICATIONS • SDH/SONET add/drop and terminal multiplexers • Linear MS/Line protection
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STM-4/OC-12
TXC-06412
VC-4-Xc/STS-1/STS-3c/STC-6c/STS9c/STS-12c
TXC-06412-MB,
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Untitled
Abstract: No abstract text available
Text: PHAST-12P Device STM-4/OC-12 SDH/SONET Overhead Terminator with CDB/PPP UTOPIA/POS-PHY Interface TXC-06412B DATA SHEET PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 FEATURES • Bit-serial LVPECL SDH/SONET line interface with integrated clock recovery and
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PHAST-12P
STM-4/OC-12
TXC-06412B
TXC-06412B-MB,
VC-4-Xc/STS-1/STS3c/STC-6c/STS-9c/STS-12c
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cd 1619
Abstract: No abstract text available
Text: PM5357 S/UNI-622-POS PMC-Sierra,Inc. 622 Mbit/s ATM and Packet Over SONET Physical Layer Device FEATURES GENERAL ATM and Packet over SONET/SDH POS OC-12c (622 Mbit/s) PHY Provides on-chip clock and data recovery and clock synthesis Exceeds Bellcore-GR-253 jitter
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OCR Scan
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PM5357
S/UNI-622-POS
100MHz
OC-12c
Bellcore-GR-253
S/UNI-622-POS
cd 1619
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