MoSys
Abstract: MC803128K32 pipeline burst
Text: MC803128K32 128Kx32 Pipeline Burst SRAM MOSYS • High performance, low power pipeline burst SRAM Overview The MoSys MC803128K32 is a high performance, low power pipeline-burst-SRAM PBSRAM . Fabricated using an advanced low power, high performance CMOS process, the MoSys MC803128K32 is
|
Original
|
MC803128K32
128Kx32
MC803128K32
32Kx32
64Kx32
32Kx32,
64Kx32,
MoSys
pipeline burst
|
PDF
|
T35L6432B
Abstract: No abstract text available
Text: tm TE CH Preliminary T35L6432B SYNCHRONOUS BURST SRAM 64K x 32 SRAM Pipeline and Flow-Through Burst Mode T35L6432B-4T FEATURES ¡E FT pin for user configurable pipeline or flowthrough operation. ¡E Fast Access times: - Pipeline – 3.8 / 4 / 4.5 / 5 ns - Flow-through – 9 / 10 / 11 / 12 ns
|
Original
|
T35L6432B
T35L6432B-4T
100-LEAD
T35L6432B
|
PDF
|
Untitled
Abstract: No abstract text available
Text: IDT29FCT520AT/BT/CT MULTILEVEL PIPELINE REGISTER INDUSTRIAL TEMPERATURE RANGE MULTILEVEL PIPELINE REGISTER IDT29FCT520AT/BT/CT DESCRIPTION: FEATURES: The 29FCT520T contains four 8-bit positive edge-triggered registers. These may be operated as a dual 2-level or as a single 4-level pipeline.
|
Original
|
IDT29FCT520AT/BT/CT
29FCT520T
-15mA
IDT29FCT
520AT
520BT
520CT
|
PDF
|
Untitled
Abstract: No abstract text available
Text: IDT29FCT520AT/BT/CT MULTILEVEL PIPELINE REGISTER INDUSTRIAL TEMPERATURE RANGE MULTILEVEL PIPELINE REGISTER IDT29FCT520AT/BT/CT DESCRIPTION: FEATURES: The 29FCT520T contains four 8-bit positive edge-triggered registers. These may be operated as a dual 2-level or as a single 4-level pipeline.
|
Original
|
IDT29FCT520AT/BT/CT
IDT29FCT520AT/BT/CT
-15mA
29FCT520T
IDT29FCT
SO24-2)
SO24-7)
SO24-8)
520AT
|
PDF
|
29FCT520T
Abstract: SO24-2
Text: IDT29FCT520AT/BT/CT MULTILEVEL PIPELINE REGISTER INDUSTRIAL TEMPERATURE RANGE MULTILEVEL PIPELINE REGISTER IDT29FCT520AT/BT/CT FEATURES: DESCRIPTION: − − − The 29FCT520T contains four 8-bit positive edge-triggered registers. These may be operated as a dual 2-level or as a single 4-level pipeline.
|
Original
|
IDT29FCT520AT/BT/CT
29FCT520T
-15mA
IDT29FCT
SO24-2)
SO24-7)
SO24-8)
520AT
SO24-2
|
PDF
|
520AT
Abstract: No abstract text available
Text: IDT29FCT520AT/BT/CT MULTILEVEL PIPELINE REGISTER INDUSTRIAL TEMPERATURE RANGE MULTILEVEL PIPELINE REGISTER IDT29FCT520AT/BT/CT FEATURES: DESCRIPTION: • • • • The 29FCT520T contains four 8-bit positive edge-triggered registers. These may be operated as a dual 2-level or as a single 4-level pipeline.
|
Original
|
IDT29FCT520AT/BT/CT
IDT29FCT520AT/BT/CT
-15mA
29FCT520T
IDT29FCT
520AT
520BT
520CT
|
PDF
|
PBSRAM
Abstract: MC8031
Text: M C80364K32, MC8031 28K32 6 4 K X 3 2 , 1 2 8 K X 3 2 PIPELINE BURST S R A M M o Sys 6 - - • High performance, low power pipeline burst SRAM
|
OCR Scan
|
C80364K32,
MC8031
28K32
83-133MHz
100-Pin
PBSRAM
|
PDF
|
104 white noise
Abstract: WED2DG472512V-D2
Text: White Electronic Designs WED2DG472512V-D2 ADVANCED* 16MB 4x512Kx72 SYNC BURST-PIPELINE, DUAL KEY DIMM DESCRIPTION FEATURES 4x512Kx72 Synchronous, Synchronous Burst Pipeline Architecture; Single Cycle Deselect Linear and Sequential Burst Support via MODE pin
|
Original
|
WED2DG472512V-D2
4x512Kx72)
WED2DG472512V
4x512Kx72.
14mmx20mm
WED2DG472512V5D2
200MHz
WED2DG472512V6D2
166MHz
WED2DG472512V65D2
104 white noise
WED2DG472512V-D2
|
PDF
|
Untitled
Abstract: No abstract text available
Text: White Electronic Designs WED2DG472512V-D2 ADVANCED* 16MB 4x512Kx72 SYNC BURST-PIPELINE, DUAL KEY DIMM DESCRIPTION FEATURES n 4x512Kx72 Synchronous, Synchronous Burst n Pipeline Architecture; Single Cycle Deselect n Linear and Sequential Burst Support via MODE pin
|
Original
|
WED2DG472512V-D2
4x512Kx72)
4x512Kx72
WED2DG472512V5D2
WED2DG472512V6D2
WED2DG472512V65D2
WED2DG472512V7D2
200MHz
166MHz
150MHz
|
PDF
|
29FCT520T
Abstract: SO24-2
Text: IDT29FCT520AT/BT/CT/DT MULTILEVEL PIPELINE REGISTER EXTENDED COMMERCIAL TEMPERATURE RANGE MULTILEVEL PIPELINE REGISTER IDT29FCT520AT/BT/CT/DT FEATURES: DESCRIPTION: − − − − − The 29FCT520T contains four 8-bit positive edge-triggered registers. These may be operated as a dual 2-level or as a single 4-level pipeline.
|
Original
|
IDT29FCT520AT/BT/CT/DT
29FCT520T
-15mA
P24-1)
SO24-2)
SO24-7)
SO24-8)
520AT
520BT
SO24-2
|
PDF
|
IBM041813PPL64K
Abstract: No abstract text available
Text: IBM041813PPL64K x 18Burst Pipeline Pentium , PLCC package. IBM041813PPL 64K X 18 BURST PIPELINE SRAM Features • 64K x 18 Organization • 0.5µ CMOS Technology • Registered Addresses, Data Ins, Control signals, and Outputs • Asynchronous Output Enable
|
Original
|
IBM041813PPL64K
18Burst
IBM041813PPL
i486TM
|
PDF
|
IBM041813PPL64K
Abstract: No abstract text available
Text: IBM041813PPL64K x 18Burst Pipeline Pentium , PLCC package. IBM041813PPL 64K X 18 BURST PIPELINE SRAM Features • 64K x 18 Organization • 0.5µ CMOS Technology • Registered Addresses, Data Ins, Control signals, and Outputs • Asynchronous Output Enable
|
Original
|
IBM041813PPL64K
18Burst
IBM041813PPL
i486TM
|
PDF
|
IBM041813PPL64K
Abstract: No abstract text available
Text: IBM041813PPL64K x 18Burst Pipeline Pentium , PLCC package. IBM041813PPLB 64K X 18 BURST PIPELINE SRAM Features • 64K x 18 Organization • 0.5µ CMOS Technology • Registered Addresses, Data Ins, Control signals, and Outputs • Asynchronous Output Enable
|
Original
|
IBM041813PPL64K
18Burst
IBM041813PPLB
i486TM
|
PDF
|
Untitled
Abstract: No abstract text available
Text: ^EDI EDI2DL32256V 256Kx32 Synchronous Pipeline Burst SRAM ELECTRONIC DESIGNS, INC TMS320C6x External SBSRAM Features Mem ory Solution The ED I2D L32256VxxB C is a 3.3V, 256Kx32 S ynchro DSP Memory Solution • nous Pipeline B urst SRAM constructed with tw o 256K x16
|
OCR Scan
|
EDI2DL32256V
256Kx32
TMS320C6x
L32256VxxB
TMS320C6201
TMS320C67x
150ieved
EDI2DL32256V
3/98ECO
|
PDF
|
|
|
Untitled
Abstract: No abstract text available
Text: ^EDI EDI2DL32256V 256Kx32 Synchronous Pipeline Burst SRAM ELECTRONIC DESIGNS, INC Features TMS320C6x External SBSRAM Memory Solution DSP Memory Solution The E D I2D L32256VxxB C is a 3.3V, 256K x32 S ynchro • nous Pipeline B urstS R A M constructed with tw o 256Kx16
|
OCR Scan
|
EDI2DL32256V
256Kx32
TMS320C6x
L32256VxxB
256Kx16
TMS320C6201
S320C67x
EDI2DL32256V40BI
119pinBGA
EDI2DL32256V
|
PDF
|
GS8162V72C
Abstract: GS8162V72CC GS8162V72CC-250 GS8162V72CC-300 GS8162V72CC-333
Text: Preliminary GS8162V72CC-333/300/250 333 MHz–250 MHz 1.8 V VDD 1.8 V I/O 256K x 72 18Mb S/DCD Sync Burst SRAMs 209-Bump BGA Commercial Temp Industrial Temp Features Flow Through/Pipeline Reads • FT pin for user-configurable flow through or pipeline operation
|
Original
|
GS8162V72CC-333/300/250
209-Bump
x18/x36
8162VxxC
GS8162V72C
GS8162V72CC
GS8162V72CC-250
GS8162V72CC-300
GS8162V72CC-333
|
PDF
|
G38-87
Abstract: SD732C64TQ-5
Text: [Advance Information] SD732C64 64K x 32 CMOS Synchronous Burst Pipeline SRAM Features Functional Description • +3.3V+10%, -5% Power Supply The SD732C64 is a high speed 2M, 65,536 x 32 cell, synchronous burst Pipeline CMOS Static RAM organized as 64K words by 32 bits that supports high performances
|
Original
|
SD732C64
SD732C64
10s/12ns/15ns
100-pin
SD732C64Q-5
SD732C64Q-6
SD732C64Q-7
G38-87
SD732C64TQ-5
|
PDF
|
Untitled
Abstract: No abstract text available
Text: SD732C32 32K x 32 CMOS Synchronous Burst Pipeline SRAM Features Functional Description • High Speed clock access time: 5/6/7/8ns The SD732C32 is a high speed synchronous burst Pipeline CMOS Static RAM organized as 32,768 words by 32 bits that supports both i486/PentiumTM Interleaved mode
|
Original
|
SD732C32
SD732C32
i486/PentiumTM
680X0/Power
SD732C32TQ-7
SD732C32TQ-8
100-pin
SD732C32Q-5
SD732C32Q-6
SD732C32Q-7
|
PDF
|
Untitled
Abstract: No abstract text available
Text: tm TE CH Preliminary T35L3232B SYNCHRONOUS BURST SRAM 32K x 32 SRAM FEATURES GENERAL DESCRIPTION ¡E FT pin for user configurable pipeline or flow-through operation. ¡E Fast Access times: - Pipeline – 3.8 / 4 / 4.5 ns - Flow-through – 9 / 10 / 11ns ¡ESingle 3.3V +0.3V/-0.165V power supply
|
Original
|
T35L3232B
|
PDF
|
GS8162V18B
Abstract: GS8162V36B
Text: Preliminary GS8162V18/36BB 119-Bump BGA Commercial Temp Industrial Temp 1M x 18, 512K x 36 18Mb S/DCD Sync Burst SRAMs Features 250 MHz–150 MHz 1.8 V VDD 1.8 V I/O Flow Through/Pipeline Reads • FT pin for user-configurable flow through or pipeline operation
|
Original
|
GS8162V18/36BB
119--Bump
x18/x36
GS8162V18B
GS8162V36B
|
PDF
|
T35L3232B-4T
Abstract: T35L3232B "32K x 32" SRAM
Text: tm TE CH Preliminary T35L3232B SYNCHRONOUS BURST SRAM 32K x 32 SRAM FEATURES GENERAL DESCRIPTION ¡E FT pin for user configurable pipeline or flow-through operation. ¡E Fast Access times: - Pipeline – 3.8 / 4 / 4.5 ns - Flow-through – 9 / 10 / 11ns ¡ESingle 3.3V +0.3V/-0.165V power supply
|
Original
|
T35L3232B
T35L3232B-4T
T35L3232B
"32K x 32" SRAM
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 3.3V CMOS 18-BIT PIPELINE REGISTERED TRANSCEIVER DESCRIPTION: FEATURES: These 18-bit pipeline registered transceivers are built us ing advanced dual metal CMOS technology. These high speed transceivers include a four deep pipelined register in the B to A direction allowing high speed burst operation. A single reg
|
OCR Scan
|
18-BIT
IDT74ALVCH1
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Product Preview GS832218 B/E /GS832236(B/E)/GS832272(C) 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs 119-, 165-, & 209-Pin BGA Commercial Temp Industrial Temp Features Flow Through/Pipeline Reads • FT pin for user-configurable flow through or pipeline operation
|
Original
|
GS832218
/GS832236
/GS832272
209-Pin
133MHz
x18/x36
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Product Preview GS864418 B/E /GS864436(B/E)/GS864472(C) 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs 119-, 165-, & 209-Pin BGA Commercial Temp Industrial Temp Features Flow Through/Pipeline Reads • FT pin for user-configurable flow through or pipeline operation
|
Original
|
GS864418
/GS864436
/GS864472
209-Pin
133MHz
x18/x36
8644xx
|
PDF
|
