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    PIN DIAGRAM OF QUAD NAND Search Results

    PIN DIAGRAM OF QUAD NAND Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    5400/BCA Rochester Electronics LLC NAND GATE; QUAD 2-INPUT Visit Rochester Electronics LLC Buy
    CS-DSDMDB09MF-010 Amphenol Cables on Demand Amphenol CS-DSDMDB09MF-010 9-Pin (DB9) Deluxe D-Sub Cable - Copper Shielded - Male / Female 10ft Datasheet
    CS-DSDMDB15MF-002.5 Amphenol Cables on Demand Amphenol CS-DSDMDB15MF-002.5 15-Pin (DB15) Deluxe D-Sub Cable - Copper Shielded - Male / Female 2.5ft Datasheet
    CS-DSDMDB15MM-025 Amphenol Cables on Demand Amphenol CS-DSDMDB15MM-025 15-Pin (DB15) Deluxe D-Sub Cable - Copper Shielded - Male / Male 25ft Datasheet
    CS-DSDMDB25MM-010 Amphenol Cables on Demand Amphenol CS-DSDMDB25MM-010 25-Pin (DB25) Deluxe D-Sub Cable - Copper Shielded - Male / Male 10ft Datasheet

    PIN DIAGRAM OF QUAD NAND Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    HEF4093BP

    Abstract: HEF4093BP datasheet free download 001aag104 HEF4093B HEF4093BT MO-001
    Text: HEF4093B Quad 2-input NAND Schmitt trigger Rev. 06 — 2 December 2009 Product data sheet 1. General description The HEF4093B is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches at different points for positive-going and negative-going signals. The


    Original     		PDF HEF4093B HEF4093B HEF4093BP HEF4093BP datasheet free download 001aag104 HEF4093BT MO-001

    HEF4093BP

    Abstract: HEF4093BP datasheet free download HEF4093BT HEF4093B MO-001
    Text: HEF4093B Quad 2-input NAND Schmitt trigger Rev. 05 — 28 July 2009 Product data sheet 1. General description The HEF4093B is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches at different points for positive-going and negative-going signals. The


    Original     		PDF HEF4093B HEF4093B HEF4093BP HEF4093BP datasheet free download HEF4093BT MO-001

    HEF4093BP

    Abstract: HEF4093BT NXP HEF4093BT MO-001 HEF4093B JESD22-A114E
    Text: HEF4093B Quad 2-input NAND Schmitt trigger Rev. 04 — 12 June 2008 Product data sheet 1. General description The HEF4093B is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches at different points for positive-going and negative-going signals. The


    Original     		PDF HEF4093B HEF4093B HEF4093BP HEF4093BT NXP HEF4093BT MO-001 JESD22-A114E

    Untitled

    Abstract: No abstract text available
    Text: IDT74LVC38A 3.3V CMOS QUAD 2-INPUT NAND GATE OPEN DRAIN EXTENDED COMMERCIAL TEMPERATURE RANGE IDT74LVC38A ADVANCE INFORMATION 3.3V CMOS QUAD 2-INPUT NAND GATE (OPEN DRAIN) WITH 5 VOLT TOLERANT I/O DESCRIPTION FEATURES: – – 0.5 MICRON CMOS Technology


    Original     		PDF IDT74LVC38A MIL-STD-883, 200pF, DT74LVC38A SO14-1) SO14-2) SO14-3)

    AHCT00

    Abstract: 74AHC00D 74AHC00 74AHC00BQ 74AHC00PW 74AHCT00 TSSOP14
    Text: 74AHC00; 74AHCT00 Quad 2-input NAND gate Rev. 04 — 28 April 2008 Product data sheet 1. General description The 74AHC00; 74AHCT00 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC


    Original     		PDF 74AHC00; 74AHCT00 74AHCT00 74AHC00: 74AHCT00: EIA/JESD22-A114E EIA/JESD22-A115-A AHCT00 74AHC00D 74AHC00 74AHC00BQ 74AHC00PW TSSOP14

    Untitled

    Abstract: No abstract text available
    Text: HEF4011B-Q100 Quad 2-input NAND gate Rev. 1 — 26 June 2013 Product data sheet 1. General description The HEF4011B-Q100 is a quad 2-input NAND gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance.


    Original     		PDF HEF4011B-Q100 HEF4011B-Q100 AEC-Q100

    dhvqfn14

    Abstract: 74AHC00 74AHC00BQ 74AHC00D 74AHC00PW 74AHCT00 74AHCT00D 74AHCT00PW JESD22-A114E
    Text: 74AHC00; 74AHCT00 Quad 2-input NAND gate Rev. 03 — 8 January 2008 Product data sheet 1. General description The 74AHC00; 74AHCT00 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . They are specified in compliance with JEDEC


    Original     		PDF 74AHC00; 74AHCT00 74AHCT00 74AHC00 JESD22-A114E JESD22-A115-A dhvqfn14 74AHC00BQ 74AHC00D 74AHC00PW 74AHCT00D 74AHCT00PW

    74hc00

    Abstract: TTL 74HC00 74HCT00 74HCT00N 74HC00DB 74HCT00D 74HCT00DB 74HC00 B1 74HC00N function table 74HC00 ordering information
    Text: 74HC00; 74HCT00 Quad 2-input NAND gate Rev. 04 — 11 January 2010 Product data sheet 1. General description The 74HC00; 74HCT00 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .


    Original     		PDF 74HC00; 74HCT00 74HCT00 74HC00: 74HCT00: JESD22-A114F JESD22-A115-A 74hc00 TTL 74HC00 74HCT00N 74HC00DB 74HCT00D 74HCT00DB 74HC00 B1 74HC00N function table 74HC00 ordering information

    74HC00

    Abstract: 74HCT00 74LV00 74LV00BQ 74LV00D 74LV00DB 74LV00N 74LV00PW JESD22-A114E 74LV001
    Text: 74LV00 Quad 2-input NAND gate Rev. 03 — 20 December 2007 Product data sheet 1. General description The 74LV00 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC00 and 74HCT00. The 74LV00 provides a quad 2-input NAND function.


    Original     		PDF 74LV00 74LV00 74HC00 74HCT00. JESD22-A114E JESD22-A115-A 74HCT00 74LV00BQ 74LV00D 74LV00DB 74LV00N 74LV00PW 74LV001

    HEF4011BP

    Abstract: HEF4011BT HEF4011B MO-001 NXP HEF4011BP
    Text: HEF4011B Quad 2-input NAND gate Rev. 4 — 30 March 2011 Product data sheet 1. General description The HEF4011B is a quad 2-input NAND gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS


    Original     		PDF HEF4011B HEF4011B HEF4011BP HEF4011BT MO-001 NXP HEF4011BP

    Untitled

    Abstract: No abstract text available
    Text: 74LV00 Quad 2-input NAND gate Rev. 03 — 20 December 2007 Product data sheet 1. General description The 74LV00 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC00 and 74HCT00. The 74LV00 provides a quad 2-input NAND function.


    Original     		PDF 74LV00 74LV00 74HC00 74HCT00. JESD22-A114E JESD22-A115-A

    74HC132

    Abstract: 74VHC132 74VHC132M 74VHC132MTC 74VHC132MTCX 74VHC132MX 74VHC132SJ M14A VHC00 VHC132
    Text: 74VHC132 Quad 2-Input NAND Schmitt Trigger tm Features General Description • High Speed: tPD = 3.9ns Typ. at VCC = 5V ■ Power down protection is provided on all inputs The VHC132 is an advanced high speed CMOS 2-input NAND Schmitt Trigger Gate fabricated with silicon gate


    Original     		PDF 74VHC132 VHC132 VHC00 74VHC132 74HC132 74VHC132M 74VHC132MTC 74VHC132MTCX 74VHC132MX 74VHC132SJ M14A

    HEF4093BP

    Abstract: HEF4093BP free HEF4093BT aSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER IN HEF4093BP datasheet free download HEF4093B MO-001 HEF4093 HEF40 Multivibrators
    Text: HEF4093B Quad 2-input NAND Schmitt trigger Rev. 7 — 1 September 2010 Product data sheet 1. General description The HEF4093B is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches at different points for positive-going and negative-going signals. The


    Original     		PDF HEF4093B HEF4093B HEF4093BP HEF4093BP free HEF4093BT aSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER IN HEF4093BP datasheet free download MO-001 HEF4093 HEF40 Multivibrators

    Untitled

    Abstract: No abstract text available
    Text: 74AHC132; 74AHCT132 Quad 2-input NAND Schmitt trigger Rev. 06 — 4 May 2009 Product data sheet 1. General description The 74AHC132; 74AHCT132 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard


    Original     		PDF 74AHC132; 74AHCT132 74AHCT132 AHCT132

    74LVC132A

    Abstract: 74LVC132ABQ 74LVC132AD 74LVC132APW TSSOP14
    Text: 74LVC132A Quad 2-input NAND Schmitt trigger Rev. 01 — 15 December 2006 Product data sheet 1. General description The 74LVC132A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC132A provides four 2-input NAND gates with Schmitt trigger inputs. It is


    Original     		PDF 74LVC132A 74LVC132A 74LVC132ABQ 74LVC132AD 74LVC132APW TSSOP14

    Untitled

    Abstract: No abstract text available
    Text: HEF4011B Quad 2-input NAND gate Rev. 5 — 21 November 2011 Product data sheet 1. General description The HEF4011B is a quad 2-input NAND gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS


    Original     		PDF HEF4011B HEF4011B

    ahct132

    Abstract: 74AHC132 74AHC132BQ 74AHC132D 74AHC132PW 74AHCT132 TSSOP14
    Text: 74AHC132; 74AHCT132 Quad 2-input NAND Schmitt trigger Rev. 06 — 4 May 2009 Product data sheet 1. General description The 74AHC132; 74AHCT132 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard


    Original     		PDF 74AHC132; 74AHCT132 74AHCT132 AHCT132 74AHC132 74AHC132BQ 74AHC132D 74AHC132PW TSSOP14

    Untitled

    Abstract: No abstract text available
    Text: 74ALVC00-Q100 Quad 2-input NAND gate Rev. 1 — 16 May 2014 Product data sheet 1. General description The 74ALVC00-Q100 is a quad 2-input NAND gate. Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times. This product has been qualified to the Automotive Electronics Council AEC standard


    Original     		PDF 74ALVC00-Q100 74ALVC00-Q100 AEC-Q100

    74HC132

    Abstract: 74HCT132 74LV132 74LV132BQ 74LV132D 74LV132DB 74LV132N 74LV132PW JESD22-A114E
    Text: 74LV132 Quad 2-input NAND Schmitt trigger Rev. 04 — 12 November 2007 Product data sheet 1. General description The 74LV132 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC132 and 74HCT132. The 74LV132 contains four 2-input NAND gates which accept standard input signals.


    Original     		PDF 74LV132 74LV132 74HC132 74HCT132. 74HCT132 74LV132BQ 74LV132D 74LV132DB 74LV132N 74LV132PW JESD22-A114E

    74AHC132

    Abstract: 74AHC132BQ 74AHC132D 74AHC132PW 74AHCT132 TSSOP14
    Text: 74AHC132; 74AHCT132 Quad 2-input NAND Schmitt trigger Rev. 05 — 9 May 2008 Product data sheet 1. General description The 74AHC132; 74AHCT132 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard


    Original     		PDF 74AHC132; 74AHCT132 74AHCT132 AHCT132 74AHC132 74AHC132BQ 74AHC132D 74AHC132PW TSSOP14

    HEF4011bp applications

    Abstract: hef4011bt NXP HEF4011BP HEF4011BP
    Text: HEF4011B Quad 2-input NAND gate Rev. 5 — 21 November 2011 Product data sheet 1. General description The HEF4011B is a quad 2-input NAND gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS


    Original     		PDF HEF4011B HEF4011B HEF4011bp applications hef4011bt NXP HEF4011BP HEF4011BP

    IC 74HC00

    Abstract: No abstract text available
    Text: 74HC00-Q100; 74HCT00-Q100 Quad 2-input NAND gate Rev. 1 — 12 July 2012 Product data sheet 1. General description The 74HC00-Q100; 74HCT00-Q100 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL


    Original     		PDF 74HC00-Q100; 74HCT00-Q100 74HCT00-Q100 AEC-Q100 74HC00-Q100: IC 74HC00

    Untitled

    Abstract: No abstract text available
    Text: HEF4093B-Q100 Quad 2-input NAND Schmitt trigger Rev. 1 — 12 July 2012 Product data sheet 1. General description The HEF4093B-Q100 is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches at different points for positive-going and negative-going signals.


    Original     		PDF HEF4093B-Q100 HEF4093B-Q100

    Untitled

    Abstract: No abstract text available
    Text: 3.3V CMOS QUAD 2-INPUT NAND GATE OPEN DRAIN , 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 1.27mm pitch SOIC, 0.65mm pitch SSOP and 0.65mm pitch TSSOP packages


    OCR Scan     		PDF MIL-STD-883, 200pF, IDT74LVC38A LVC38A tPLH11