C2048
Abstract: No abstract text available
Text: LUPA-4000 4M Pixel CMOS Image Sensor SPI interface. It is housed in a 127-pin ceramic PGA package. This data sheet allows the user to develop a camera-system based on the described timing and interfacing. Main features Preamble The main features of the image sensor are identified as:
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LUPA-4000
127-pin
LUPA-4000
C2048
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LUPA-4000-M
Abstract: FillFactory CYIL1SM4000AA-GBC CYIL1SM4000AA-GDC JESD22 LUPA-4000 L2048 Linear Image Sensor 2048 schematic
Text: LUPA-4000 4M Pixel CMOS Image Sensor SPI interface. It is housed in a 127-pin ceramic PGA package. This data sheet allows the user to develop a camera-system based on the described timing and interfacing. Main features Preamble The main features of the image sensor are identified as:
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LUPA-4000
127-pin
LUPA-4000
LUPA-4000-M
FillFactory
CYIL1SM4000AA-GBC
CYIL1SM4000AA-GDC
JESD22
L2048
Linear Image Sensor 2048 schematic
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dual tracking linear power supply
Abstract: analog pixel driver CMOS 4000 rgb sensor board 1394 schematic alcohol sensor data sheet Chip Resistors Parasitic capacitance CMOS digital image sensor CMOS digital image sensor with global shutter CMOS image sensor with global shutter
Text: LUPA-4000 4M Pixel CMOS Image Sensor SPI interface. It is housed in a 127-pin ceramic PGA package. This data sheet allows the user to develop a camera-system based on the described timing and interfacing. Main features Preamble The main features of the image sensor are identified as:
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LUPA-4000
127-pin
LUPA-4000
dual tracking linear power supply
analog pixel driver
CMOS 4000
rgb sensor board
1394 schematic
alcohol sensor data sheet
Chip Resistors Parasitic capacitance
CMOS digital image sensor
CMOS digital image sensor with global shutter
CMOS image sensor with global shutter
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BC 1098
Abstract: EPM7384 ALTERA 68 PLCC t187
Text: Altera Device Package Information June 1998, ver. 7.01 Introduction Data Sheet This data sheet provides the following package information for all Altera¨ devices: • ■ ■ ■ Lead materials Thermal resistance Package weights Package outlines In this data sheet, packages are listed in order of ascending pin count.
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232-pin
240-pin
100-pin
256-pin
484-pin
672-pin
BC 1098
EPM7384
ALTERA 68 PLCC
t187
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100 PIN "PGA" ALTERA DIMENSION
Abstract: No abstract text available
Text: Altera Device Package Information June 1996, ver. 6 Introduction Data Sheet This data sheet provides the following package information for all Altera devices: • ■ ■ ■ Lead materials Thermal resistance Package weights Package outlines In this data sheet, packages are listed in ascending pin count order.
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altera ep610
Abstract: EPM5130 240 PIN QFP ALTERA DIMENSION epm7064s cross reference 192PGA EPF10K100 EPF10K20 EPF10K30 EPF10K40 EPF10K50
Text: Altera Device Package Information June 1996, ver. 6 Introduction Data Sheet This data sheet provides the following package information for all Altera devices: • ■ ■ ■ Lead materials Thermal resistance Package weights Package outlines In this data sheet, packages are listed in ascending pin count order.
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transistors BC 458
Abstract: 240 pin rqfp drawing ep600i BC 458 256-pin BGA drawing EPM7032-44 transistor BC 458 tqfp 44 thermal resistance datasheet epm7064s cross reference BGA PACKAGE thermal resistance
Text: Altera Device Package Information August 1999, ver. 8 Data Sheet 2 Introduction This data sheet provides the following package information for all Altera® devices: • ■ ■ ■ Lead materials Thermal resistance Package weights Package outlines In this data sheet, packages are listed in order of ascending pin count.
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EP20K100E
Abstract: EP20K160E EP20K200 EP20K200E EP20K300E EP20K60E EP20K100 0245 TQFP-208 208RQFP 280-PGA
Text: Altera Device Package Information August 2000, ver. 8.03 Data Sheet 2 Introduction This data sheet provides the following package information for all Altera® devices: • ■ ■ ■ Lead materials Thermal resistance Package weights Package outlines In this data sheet, packages are listed in order of ascending pin count.
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49-pin
169-pin
EP20K100E
EP20K160E
EP20K200
EP20K200E
EP20K300E
EP20K60E
EP20K100
0245 TQFP-208
208RQFP
280-PGA
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ep600i
Abstract: JEDEC MS-034-AAJ-1 BGA Package 172 EP1800 MS-034 AAF-1 192PGA pdip 24 altera AP672 EP610 epm9560 die
Text: Altera Device Package Information May 2001, ver. 9.1 Introduction Data Sheet This data sheet provides the following package information for all Altera® devices: • ■ ■ ■ Lead materials Thermal resistance Package weights Package outlines In this data sheet, packages are listed in order of ascending pin count.
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208 pin rqfp drawing
Abstract: 240 pin rqfp drawing BGA 144 MS-034 AAL-1 bga package weight 192 BGA PACKAGE thermal resistance
Text: Altera Device Package Information April 2002, ver. 10.2 Introduction Data Sheet This data sheet provides the following package information for all Altera devices: • ■ ■ ■ Lead materials Thermal resistance Package weights Package outlines In this data sheet, packages are listed in order of ascending pin count.
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Untitled
Abstract: No abstract text available
Text: EPM 7256E EPLD Features □ Preliminary Information □ O O O □ High-density, erasable CMOS EPLD based on second-generation Multiple Array Matrix MAX architecture 5,000 usable gates Combinatorial speeds with tPD = 12 ns Counter frequencies up to 90.9 MHz
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7256E
192-pin
208-pin
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48-MACROCELL
Abstract: No abstract text available
Text: EP1810 EPLD Features ^ High-performance, 48-macrocell Classic EPLD Combinatorial speeds with tPD = 20,25,35, and 45 ns Counter frequencies up to 50 MHz Pipelined data rates up to 62.5 MHz Programmable I/O architecture with up to 64 inputs or 48 outputs Pin-, function-, and programming file-compatible with Altera's
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EP1810
48-macrocell
EP1810T
MIL-STD-883-compliant
68-pin
ALTED001
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7400 series TTL pinouts
Abstract: EPLD 5128
Text: EPM 5128 EPLD Features □ □ High-density 128-macrocell general-purpose M AX 5000 EPLD 256 shareable expander product terms that allow over 32 product terms in a single macrocell High-speed multi-LAB architecture tPD as fast as 25 ns Counter frequencies up to 50 MHz
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128-macrocell
68-pin
5000-family
7400 series TTL pinouts
EPLD 5128
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B1142
Abstract: No abstract text available
Text: E P 1810 E P L D Features * High-performance, 48-macrocell Classic EPLD Combinatorial speeds with t PD as fast as 20 ns Counter frequencies of up to 50 MHz Pipelined data rates of up to 62.5 MHz Programmable I/O architecture with up to 64 inputs or 48 outputs
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48-macrocell
68-pin
EP1810
B1142
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208 pin rqfp drawing
Abstract: 240 pin rqfp drawing ALTERA flex 81188 altera 5032 8636a EPF81188AGC232-3 100 PIN "PGA" ALTERA DIMENSION 5130a PL-SKT/Q160 Altera EPC
Text: y /^ \ [^ V a \ Ordering Information M a rc h 19 95, ver. 7 Altera DBViC6S Figure 1 explains the ordering codes for Altera devices. Devices that have multiple pin counts for the same package include the pin count in their ordering codes. Some codes use relative numbers e.g., -1, -2 to designate
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208-pin
240-pin
304-pin
PL-SKT/Q100
PL-SKT/Q160
PL-SKT/Q208
PL-SKT/Q240
PL-SKT/Q304
100-pin
208 pin rqfp drawing
240 pin rqfp drawing
ALTERA flex 81188
altera 5032
8636a
EPF81188AGC232-3
100 PIN "PGA" ALTERA DIMENSION
5130a
Altera EPC
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C2657
Abstract: EPI810 K102-8 EP181B
Text: EP1810 EPLD Features • ■ ■ ■ ■ High-performance, 48-macrocell Classic EPLD Combinatorial speeds with tPD as fast as 20 ns - Counter frequencies of up to 50 MHz - Pipelined data rates of up to 62.5 MHz Programmable I/O architecture with up to 64 inputs or 48 outputs
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EP1810
48-macrocell
68-pin
C2657
EPI810
K102-8
EP181B
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IOG11
Abstract: H10IO K1026
Text: AL TE RA CORP bäE » • D S R S 3 7 S Ü Ü G B M O R Û7Ô ALT EP1810 EPLD Features ^ □ □ □ □ □ High-performance, 48-macrocell Classic EPLD Combinatorial speeds with tPD = 20,25,35, and 45 ns Counter frequencies up to 50 MHz Pipelined data rates up to 62.5 MHz
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SRS37S
EP1810
48-macrocell
EP1810T
MIL-STD-883-compliant
68-pin
IOG11
H10IO
K1026
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4572 smd 8pin
Abstract: 100 PIN "PGA" ALTERA DIMENSION CMGA17-P100E 02D-00194 altera 24pin dip drawing
Text: Altera Device Package Outlines March 1995, ver. 5 In tro d u c tio n Data Sheet This data sheet provides package outlines for all Altera devices. Package outlines are listed here in ascending pin count order. Table 1 summarizes the maximum lead coplanarity for Altera J-lead and QFP packages:
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304-Pin
560-Pin
4572 smd 8pin
100 PIN "PGA" ALTERA DIMENSION
CMGA17-P100E
02D-00194
altera 24pin dip drawing
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Untitled
Abstract: No abstract text available
Text: EP1810 EPLD Features • ■ ■ ■ High-performance, 48-macrocell Classic EPLD Combinatorial speeds with t P D as fast as 20 ns Counter frequencies of up to 50 MHz Pipelined data rates of up to 62.5 MHz Programmable I/O architecture with up to 64 inputs or 48 outputs
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EP1810
48-macrocell
68-pin
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EP1800I
Abstract: Altera EP1800i
Text: E P 1810 E P L D Features 11 High-performance, 48-macrocell Classic EPLD Combinatorial speeds with tPD as low as 20 ns Counter frequencies of up to 50 MHz Pipelined data rates of up to 62.5 MHz Programmable I/O architecture with up to 64 inputs or 48 outputs
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48-macrocell
EP1810
EP1800I
68-pin
Diagr810
Altera EP1800i
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EPLD 5128
Abstract: EPM5128-1 K942
Text: EPM5128 EPLD Features □ □ □ □ □ H igh-density, 128-macrocell, general-purpose MAX 5000 EPLD High-speed multi-LAB architecture t PD as fast as 25 ns Counter frequencies up to 50 MHz Pipelined data rates up to 62.5 MHz 256 shareable expander product terms "expanders" allowing over
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EPM5128
128-macrocell,
68-pin
ALTED001
EPLD 5128
EPM5128-1
K942
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EPM 5192
Abstract: EPM5192
Text: EPM5192 EPLD Features H igh-density, 192 macrocell, general-purpose MAX 5000 EPLD, easily integrating com plete logic boards into a single package High-speed multi-LAB architecture t PD as fast as 25 ns Counter frequencies up to 50 MHz Pipelined data rates up to 62.5 MHz
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EPM5192
EPM519-
84-Pin
ALTED001
EPM 5192
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Altera EP1810
Abstract: MIL-STD-883-compliant
Text: EP1810 MIL-STD-883-Compliant EPLD Features □ □ □ □ □ High-performance, 48-macrocell Classic EPLD Combinatorial speeds with tPD = 45 ns Counter frequencies up to 22.2 MHz Pipelined data rates up to 33.3 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs
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EP1810
MIL-STD-883-Compliant
48-macrocell
EP1810T
68-pin
ALTED001
Altera EP1810
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K 7256 M
Abstract: EPM7256 PIN
Text: EPM7256 EPLD □ Features □ □ □ □ □ High-density, erasable CM OS EPLD based on second-generation MAX architecture 5,000 usable gates Combinatorial speeds with t P D = 20 ns Higher speed versions under development Counter frequencies up to 62.5 MHz
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EPM7256
192-pin
208-pin
in-Out02
ALTED001
K 7256 M
EPM7256 PIN
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