QL3012
Abstract: PF100 PF144 PL84 QL3012-1PF100C QL3012-1PQ144C
Text: QL3012 - pASIC 3 FPGATM 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density QL3012 - pASIC 3 FPGA DEVICE HIGHLIGHTS Device Highlights High Performance & High Density • 12,000 Usable PLD Gates with 118 I/Os ■ 16-bit counter speeds over 300 MHz, data path speeds over
|
Original
|
QL3012
16-bit
PF100
PF144
PL84
QL3012-1PF100C
QL3012-1PQ144C
|
PDF
|
ad 161
Abstract: vhdl code PN code generator ad 152 transistor ad 153 transistor S-108 PF144 PQ208 QL5130 QL5130-33APF144C QL5130-33APQ208C
Text: QL5130 - QuickPCITM 33 MHz/32-bit PCI Target with Embedded Programmable Logic and Dual Port SRAM last updated 12/1099 Device Highlights DEVICE HIGHLIGHTS Q8DÃ7ñÃ""ÃHCÃ"!ÃivÃqhhÃhqÃhqq
r High Performance PCI Controller • 32-bit / 33 MHz PCI Target
|
Original
|
QL5130
Hz/32-bit
32-bit
95/98/Win
ad 161
vhdl code PN code generator
ad 152 transistor
ad 153 transistor
S-108
PF144
PQ208
QL5130-33APF144C
QL5130-33APQ208C
|
PDF
|
Untitled
Abstract: No abstract text available
Text: QL2009 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. C pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance
|
Original
|
QL2009
|
PDF
|
74 164 14 PIN DIAGRAM
Abstract: QL5022 QL5022-33APQ208C QL5022-33BPF144C PCI32 PF144 PQ208
Text: QL5022 QuickPCI Data Sheet •••••• 33 MHz/32-bit PCI Host Capable Master Target with Embedded Programmable Logic Device Highlights Programmable Logic • 387 Logic Cells High Performance PCI Controller • 32-bit / 33 MHz PCI Master/Target with
|
Original
|
QL5022
Hz/32-bit
32-bit
95/98/Win
2000/NT4
74 164 14 PIN DIAGRAM
QL5022-33APQ208C
QL5022-33BPF144C
PCI32
PF144
PQ208
|
PDF
|
16X24B
Abstract: CF160 PF100 PF144 PL84 CPGA Package Diagram
Text: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.
|
Original
|
QL16x24B
16-by-24
84-pin
100-pin
144-pin
160-pin
16-bit
16x24B
CF160
PF100
PF144
PL84
CPGA Package Diagram
|
PDF
|
PL84
Abstract: ql16x24bl PF100 PF144
Text: QL16x24BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5V Tolerant I/Os – Support interface to 5 Volt CMOS, NMOS and
|
Original
|
QL16x24BL
16-by-24
84-pin
100-pin
144-pin
QL16x24B
QL16x24
16x24BL
PF144
84-pin
PL84
ql16x24bl
PF100
|
PDF
|
quickpro
Abstract: PF144 PQ208 QL5020
Text: QL5020 QuickPCI Data Sheet •••••• 33 MHz/32-bit PCI with Embedded Programmable Logic Device Highlights Programmable Logic • 560 Logic Cells High Performance PCI Controller • 32-bit/33 MHz PCI Target with Embedded • • • • • • •
|
Original
|
QL5020
Hz/32-bit
32-bit/33
95/98/Win
2000/NT4
quickpro
PF144
PQ208
|
PDF
|
QL4090
Abstract: pASIC 1 Family 160CQFP 208-CQFP
Text: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.
|
Original
|
QL16x24B
16-by-24
84-pin
100-pin
144-pin
160-pin
16-bit
V144-TQFP
QL24x32B
QL4090
pASIC 1 Family
160CQFP
208-CQFP
|
PDF
|
208CQFP
Abstract: No abstract text available
Text: QL2007 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. E pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance
|
Original
|
QL2007
-16-bit
l144-TQFP
QL24x32B
208-PQFP
208-CQFP
125oC
MIL-STD-883
208CQFP
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Eclipse II Family Data Sheet • • • • • • Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Multiple dedicated low skew clock networks Flexible Programmable Logic • High drive input-only networks
|
Original
|
|
PDF
|
Untitled
Abstract: No abstract text available
Text: QL58x2 Enhanced QuickPCI Family Data Sheet • • • • • • 33/66 MHz/32-bit PCI Master/Target with Embedded Programmable Logic, Embedded Computational Units, and Dual Port SRAM Device Highlights Extendable PCI Functionality High Performance PCI Controller
|
Original
|
QL58x2
Hz/32-bit
32-bit
|
PDF
|
Untitled
Abstract: No abstract text available
Text: QuickLogic PolarPro Data Sheet • • • • • • Combining Low Power, Performance, Density, and Embedded RAM Device Highlights 4 programmable global clock networks • Quadrant-based segmentable clock networks Low Power Programmable Logic 20 quad clock networks per device
|
Original
|
|
PDF
|
Untitled
Abstract: No abstract text available
Text: QL3012 - pASIC 3 FPGATM 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density last updated 5/17/2000 QL3012 - pASIC 3 FPGA DEVICE HIGHLIGHTS Device Highlights High Performance & High Density • 12,000 Usable PLD Gates with 118 I/Os
|
Original
|
QL3012
16-bit
|
PDF
|
Untitled
Abstract: No abstract text available
Text: QL4016 QuickRAM Data Sheet • • • • • • 16,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM Device Highlights Advanced I/O Capabilities • Interfaces with both 3.3 V and 5.0 V devices High Performance & High Density
|
Original
|
QL4016
16-bit
|
PDF
|
|
|
PF144
Abstract: PQ208 QL24X32B-1PQ208C
Text: QL24x32B pASIC 1 Family Very-High-Speed CMOS FPGA pASIC HIGHLIGHTS …8,000 usable ASIC gates, 180 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.
|
Original
|
QL24x32B
24-by-32
144-pin
208-pin
24x32B
PQ208
M/883C
PF144
PF144
QL24X32B-1PQ208C
|
PDF
|
PF144
Abstract: PQ208 QL2009 QL2009-1PB256C QL2009-1PF144C QL2009-1PQ208C
Text: QL2009 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. C pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance
|
Original
|
QL2009
PF144
PQ208
QL2009
QL2009-1PB256C
QL2009-1PF144C
QL2009-1PQ208C
|
PDF
|
QL1P100
Abstract: No abstract text available
Text: QuickLogic PolarPro Device Data Sheet — QL1P075, QL1P100, QL1P200, and QL1P300 •••••• Combining Low Power, Performance, Density, and Embedded RAM • Quadrant-based segmentable clock networks Device Highlights 20 quad clock networks per device
|
Original
|
QL1P075,
QL1P100,
QL1P200,
QL1P300
QL1P100
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Eclipse II Family Data Sheet • • • • • • Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Multiple dedicated low skew clock networks Flexible Programmable Logic • High drive input-only networks
|
Original
|
|
PDF
|
Untitled
Abstract: No abstract text available
Text: QL58x0 Enhanced QuickPCI Target Family Data Sheet • • • • • • 33/66 MHz/32-bit PCI Target with Embedded Programmable Logic, Embedded Computational Units, and Dual Port SRAM Device Highlights Extendable PCI Functionality High Performance PCI Controller
|
Original
|
QL58x0
Hz/32-bit
32-bit
95/98/2000/NT
484-ball
|
PDF
|
PF144
Abstract: QL5030
Text: Back QL5030 - QuickPCI ESP 33 MHz/32-bit PCI Target with Embedded Programmable Logic and Dual Port SRAM Advance Data DEVICE HIGHLIGHTS Updated: 22-Feb-99 High Performance PCI Controller - 32-bit / 33 MHz PCI Target PCI Zero-wait state PCI Target provides 132 MB/s transfer rates
|
Original
|
QL5030
Hz/32-bit
22-Feb-99
32-bit
95/98/NT4
PF144
|
PDF
|
asynchronous fifo vhdl
Abstract: 8 BIT ALU design with verilog/vhdl code full subtractor using ic 74138 74139 for bcd to excess 3 code vhdl code for 8bit bcd to seven segment display 32 BIT ALU design with verilog/vhdl code 74594 16 BIT ALU design with verilog/vhdl code B1516 RAM1024
Text: QuickWorks User Manual with SpDE Reference Release 2009.2.1 Contact Information QuickLogic Corporation 1277 Orleans Drive Sunnyvale, CA 94089 Phone: (408) 990-4000 (US) (905) 940-4149 (Canada) +(44) 1932-57-9011 (Europe) +(852) 2567-5441 (Asia) E-mail: info@quicklogic.com
|
Original
|
|
PDF
|
PF144
Abstract: QL5030 QL5030-33APF144C TQ144
Text: QL5030 QuickPCI Data Sheet • • • • • • 33 MHz/32-bit PCI Target with Embedded Programmable Logic and Dual Port SRAM 1.0 Device Highlights High Performance PCI Controller • Programmable Interrupt Generator • I2O Support with Local Processor
|
Original
|
QL5030
Hz/32-bit
32-bit
95/98/Win
2000/NT4
PF144
QL5030-33APF144C
TQ144
|
PDF
|
16X24
Abstract: No abstract text available
Text: QL16x24B/QL16x24BH WildCat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA Rev B pASIC HIGHLIGHTS B Very High Speed - V iaL ink metal-to-metal program m able-via anti fuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.
|
OCR Scan
|
QL16x24B/QL16x24BH
16-by-24
84pin
100-pin
144-pin
160pin
16-bit
QL16x24BH
16X24
|
PDF
|
QL2009
Abstract: QL2009-1PB256C QL2009-1PF144C QL2009-1PQ208C TIL405
Text: Q L2009 9,000 Gate pASIC 2 FPGA Com bining Speed, Density, Low Cost and Flexibility PRELIMINARY DA TA pASIC 2 HIGHLIGHTS E Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance
|
OCR Scan
|
QL2009
QL2009
PQ208
PF144
144-pin
PQ208
208-pin
PB256
256-pin
0000b77
QL2009-1PB256C
QL2009-1PF144C
QL2009-1PQ208C
TIL405
|
PDF
|
