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    PB37A FORM W Search Results

    PB37A FORM W Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TLP3406SRH4 Toshiba Electronic Devices & Storage Corporation Photorelay (MOSFET output, 1-form-a), 30 V/0.9 A, 300 Vrms, S-VSON16T Visit Toshiba Electronic Devices & Storage Corporation
    TLP3407SRA Toshiba Electronic Devices & Storage Corporation Photorelay (MOSFET output, 1-form-a), 60 V/1 A, 500 Vrms, S-VSON4T Visit Toshiba Electronic Devices & Storage Corporation
    TLP3407SRH Toshiba Electronic Devices & Storage Corporation Photorelay (MOSFET output, 1-form-a), 60 V/1 A, 500 Vrms, S-VSON4T Visit Toshiba Electronic Devices & Storage Corporation
    TLP3412SRHA4 Toshiba Electronic Devices & Storage Corporation Photorelay (MOSFET output, 1-form-a), 60 V/0.25 A, 300 Vrms, S-VSON16T Visit Toshiba Electronic Devices & Storage Corporation
    TLP241B Toshiba Electronic Devices & Storage Corporation Photorelay (MOSFET output, 1-form-a), 100 V/2.0 A, 5000 Vrms, DIP4 Visit Toshiba Electronic Devices & Storage Corporation

    PB37A FORM W Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet Version 01.3, June 2005 LatticeXP Family Data Sheet Introduction May 2005 Advance Data Sheet Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL – SSTL 18 Class I


    Original     		PDF HSTL15 TN1052) TN1082)

    Untitled

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet Version 04.4, April 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL


    Original     		PDF HSTL15 TN1050) TN1052) TN1082)

    Untitled

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet Version 03.0, September 2005 LatticeXP Family Data Sheet Introduction July 2005 Advance Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2


    Original     		PDF HSTL15 TN1050) TN1052) TN1082)

    LFXP10C-4FN256C

    Abstract: PB27A PT15B LFXP15C-5FN388C LFXP10C5FN256C LFXP3C-3QN208C LFXP6C-5FN256C LFXP10C-4FN388C LFXP6C-5TN144C LFXP20C-5FN484C
    Text: LatticeXP Family Data Sheet Version 04.5, May 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL


    Original     		PDF HSTL15 1000x TN1051) TN1050) TN1052) TN1082) LFXP10C-4FN256C PB27A PT15B LFXP15C-5FN388C LFXP10C5FN256C LFXP3C-3QN208C LFXP6C-5FN256C LFXP10C-4FN388C LFXP6C-5TN144C LFXP20C-5FN484C

    Untitled

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet DS1001 Version 04.7, August 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2


    Original     		PDF DS1001 DS1001 HSTL15 LVDS25E

    Untitled

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet DS1001 Version 05.0, July 2007 LatticeXP Family Data Sheet Introduction July 2007 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2


    Original     		PDF DS1001 DS1001 HSTL15 1000x

    LFXP3C-3TN144C

    Abstract: LFXP6C-4FN256C 3FN3 LFXP3C-3TN100C LFXP6C-3FN256I PT36 LFXP10C-3F256I LFXP3C-4TN100C LFXP15C-5FN388C LFXP6
    Text: LatticeXP Family Data Sheet DS1001 Version 05.1, November 2007 LatticeXP Family Data Sheet Introduction July 2007 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2


    Original     		PDF DS1001 DS1001 HSTL15 LVDS25E LFXP3C-3TN144C LFXP6C-4FN256C 3FN3 LFXP3C-3TN100C LFXP6C-3FN256I PT36 LFXP10C-3F256I LFXP3C-4TN100C LFXP15C-5FN388C LFXP6

    PL44A

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet DS1001 Version 04.9, February 2007 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2


    Original     		PDF DS1001 DS1001 HSTL15 1000x LVDS25E PL44A

    PT15B

    Abstract: LFXP20C-5FN484C
    Text: LatticeXP Family Data Sheet DS1001 Version 04.9, February 2007 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2


    Original     		PDF DS1001 DS1001 HSTL15 LVDS25E PT15B LFXP20C-5FN484C

    LFXP20C-5F256C

    Abstract: LFXP20C-4F484C PT15B
    Text: LatticeXP Family Data Sheet DS1001 Version 05.1, November 2007 LatticeXP Family Data Sheet Introduction July 2007 Data Sheet DS1001  Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces:  LVCMOS 3.3/2.5/1.8/1.5/1.2


    Original     		PDF DS1001 DS1001 HSTL15 1000x LFXP20C-5F256C LFXP20C-4F484C PT15B

    LFXP20C-4F484C

    Abstract: PT15B
    Text: LatticeXP Family Data Sheet Version 04.3, March 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL


    Original     		PDF HSTL15 1000x TN1051) TN1050) TN1052) TN1082) LFXP20C-4F484C PT15B

    Untitled

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet Version 04.0, December 2005 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL


    Original     		PDF HSTL15 TN1050) TN1052) TN1082)

    Untitled

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet Version 04.2, March 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL


    Original     		PDF HSTL15 TN1050) TN1052) TN1082)

    Untitled

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet Version 02.0, July 2005 LatticeXP Family Data Sheet Introduction July 2005 Advance Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL


    Original     		PDF HSTL15 TN1052) TN1082)

    PT15B

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet Version 04.1, February 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL


    Original     		PDF HSTL15 1000x TN1051) TN1050) TN1052) TN1082) PT15B

    LFXP20C-4F484C

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet DS1001 Version 04.6, June 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2


    Original     		PDF DS1001 DS1001 HSTL15 1000x LVDS25E LFXP20C-4F484C

    PT15B

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet DS1001 Version 04.8, December 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2


    Original     		PDF DS1001 DS1001 HSTL15 1000x LVDS25E PT15B

    Untitled

    Abstract: No abstract text available
    Text:  MachXO2 Breakout Board Evaluation Kit User’s Guide January 2014 Revision: EB68_02.2  MachXO2 Breakout Board Evaluation Kit User’s Guide Introduction Thank you for choosing the Lattice Semiconductor MachXO2 Breakout Board Evaluation Kit! This user’s guide describes how to start using the MachXO2 Breakout Board, an easy-to-use platform for evaluating and designing with the MachXO2 ultra-low density FPGA. Along with the board and accessories, this kit


    Original     		PDF MachXO2-7000HE MachXO2-12R16, RC0603JR-070RL CRCW06031R00JNEAHP RC0603FR-07100RL RC0402FR-071KL FT2232HL 93LC56C-I/SN LCMXO2-7000HE-4TG144C

    sot23 Transistor marking W18

    Abstract: EB29 LCM-S02002DSF LDS-A304RI POWR607 68013a PT38A sot marking code w17 SOT-23 a6 ZENER aa15
    Text: LatticeXP2 Standard Evaluation Board User’s Guide February 2008 Revision: EB29_01.3 LatticeXP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Introduction The LatticeXP2 Standard Evaluation Board provides a convenient platform to evaluate, test and debug user


    Original     		PDF LatticeXP2-17 soic16 8013A RS232 ADS7842 tssop16 dip14 sot23 Transistor marking W18 EB29 LCM-S02002DSF LDS-A304RI POWR607 68013a PT38A sot marking code w17 SOT-23 a6 ZENER aa15

    MP2307

    Abstract: sot marking code w17 transistor marking code w17 SOT-23 A22 MARKING soic8 PT43B transistor cf43 W17 marking code sot 23 POWR607 sma connector footprint transistor marking A9 R8
    Text:  LatticeXP2 Standard Evaluation Board User’s Guide February 2010 Revision: EB29_01.5  LatticeXP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Introduction The LatticeXP2 Standard Evaluation Board provides a convenient platform to evaluate, test and debug user


    Original     		PDF LatticeXP2-17 soic16 8013A RS232 ADS7842 tssop16 dip14 MP2307 sot marking code w17 transistor marking code w17 SOT-23 A22 MARKING soic8 PT43B transistor cf43 W17 marking code sot 23 POWR607 sma connector footprint transistor marking A9 R8

    Untitled

    Abstract: No abstract text available
    Text: LatticeSC Family Data Sheet DS1004 Version 01.5, March 2007 LatticeSC Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW LFSC25 FF1020 LFSC80

    Untitled

    Abstract: No abstract text available
    Text: LatticeSC Family Data Sheet DS1004 Version 01.5, March 2007 LatticeSC Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW LFSC25 FF1020 LFSC80

    Untitled

    Abstract: No abstract text available
    Text: LatticeSC/M Family Data Sheet DS1004 Version 01.6, August 2007 LatticeSC/M Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW

    Untitled

    Abstract: No abstract text available
    Text: LatticeSC Family Data Sheet DS1004 Version 01.5, March 2007 LatticeSC Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW LFSC25 FF1020 LFSC80