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    AA30

    Abstract: AA34 AB30 M21110 PRBS MSB NCN30
    Text: M21110 17 x 17 3.2 Gbps Crosspoint Switch with Input Equalization Data Sheet Features - 4 Terminal Descriptions - 5 Specification Tables - 7 Functional Description - 17 Register Information - 21 Package Information - 28 World Wide Sales Companies - 37 21110-DSH-001-B, 3/27/03


    Original     		PDF M21110 21110-DSH-001-B, AA30 AA34 AB30 M21110 PRBS MSB NCN30

    Untitled

    Abstract: No abstract text available
    Text: CDCLVP1216 www.ti.com . SCAS877A – MAY 2009 – REVISED JULY 2009 16 LVPECL Output, High-Performance Clock Buffer


    Original     		PDF CDCLVP1216 SCAS877A CDCLVP1216

    outp32

    Abstract: M21130 AA30 AA34 AB30 OUTP23 NCN30
    Text: M21130 68 x 68 3.2 Gbps Crosspoint Switch with Input Equalization Data Sheet Features - 4 Terminal Descriptions - 5 Specification Tables - 8 Functional Description - 17 Register Information - 20 Package Information - 25 World Wide Sales Companies - 34 21130-DSH-001-B, 3/27/03


    Original     		PDF M21130 21130-DSH-001-B, outp32 M21130 AA30 AA34 AB30 OUTP23 NCN30

    Untitled

    Abstract: No abstract text available
    Text: CDCLVD2108 www.ti.com SCAS905C – OCTOBER 2010 – REVISED DECEMBER 2010 Dual 1:8 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2108 FEATURES 1 • • • • • • • • • • • • Dual 1:8 Differential Buffer Low Additive Jitter <300 fs RMS in


    Original     		PDF CDCLVD2108 SCAS905C EIA/TIA-644A 48-Pin

    L510B

    Abstract: L61A L110 L111 l413 l812 L410A L77A L711B L713
    Text: Appl i cat i o n N ot e Designing High-Speed ATM Switch Fabrics by Using Actel FPGAs The recent upsurge of interest in Asynchronous Transfer Mode ATM is based on the recognition that it represents a new level of both speed and simplification in telecommunication networks. The most significant


    Original     		PDF OUTP10 OUTP11 OUTP12 PADOUTP13 PADOUTP14 PADOUTP15 L510B L61A L110 L111 l413 l812 L410A L77A L711B L713

    Untitled

    Abstract: No abstract text available
    Text: CDCLVP1216 SCAS877C – MAY 2009 – REVISED AUGUST 2011 www.ti.com 16 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP1216 FEATURES DESCRIPTION • • • The CDCLVP1216 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL


    Original     		PDF CDCLVP1216 SCAS877C 10-kHz 20-MHz QFN-48

    Untitled

    Abstract: No abstract text available
    Text: CDCLVP1216 SCAS877C – MAY 2009 – REVISED AUGUST 2011 www.ti.com 16 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP1216 FEATURES DESCRIPTION • • • The CDCLVP1216 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL


    Original     		PDF CDCLVP1216 SCAS877C 10-kHz 20-MHz QFN-48

    Untitled

    Abstract: No abstract text available
    Text: CDCLVD2108 www.ti.com SCAS905C – OCTOBER 2010 – REVISED DECEMBER 2010 Dual 1:8 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2108 FEATURES 1 • • • • • • • • • • • • Dual 1:8 Differential Buffer Low Additive Jitter <300 fs RMS in


    Original     		PDF CDCLVD2108 SCAS905C EIA/TIA-644A 48-Pin CDCLVD2108m/clocks

    QFN-48 LAND PATTERN

    Abstract: CDCLVP1216 CDCLVP1216RGZR CDCLVP1216RGZT QFN-48
    Text: CDCLVP1216 www.ti.com . SCAS877A – MAY 2009 – REVISED JULY 2009 16 LVPECL Output, High-Performance Clock Buffer


    Original     		PDF CDCLVP1216 SCAS877A 10-kHz 20-MHz QFN-48 LAND PATTERN CDCLVP1216 CDCLVP1216RGZR CDCLVP1216RGZT QFN-48

    CDCLVP1216

    Abstract: CDCLVP1216RGZR CDCLVP1216RGZT QFN-48
    Text: CDCLVP1216 www.ti.com . SCAS877A – MAY 2009 – REVISED JULY 2009 16 LVPECL Output, High-Performance Clock Buffer


    Original     		PDF CDCLVP1216 SCAS877A 10-kHz 20-MHz CDCLVP1216 CDCLVP1216RGZR CDCLVP1216RGZT QFN-48

    Untitled

    Abstract: No abstract text available
    Text: CDCLVD1216 www.ti.com SCAS900B – OCTOBER 2010 – REVISED JANUARY 2011 2:16 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1216 FEATURES 1 • • • • • • • • • • • • 2:16 Differential Buffer Low Additive Jitter: <300 fs RMS in


    Original     		PDF CDCLVD1216 SCAS900B EIA/TIA-644A 48-Pin

    CDCLVP2108

    Abstract: CDCLVP2108RGZR CDCLVP2108RGZT QFN-48 QFN-48 LAND PATTERN QFN-48 footprint
    Text: CDCLVP2108 www.ti.com . SCAS878A – MAY 2009 – REVISED JULY 2009 16 LVPECL Output, High-Performance Clock Buffer


    Original     		PDF CDCLVP2108 SCAS878A 10-kHz 20-MHz CDCLVP2108 CDCLVP2108RGZR CDCLVP2108RGZT QFN-48 QFN-48 LAND PATTERN QFN-48 footprint

    Untitled

    Abstract: No abstract text available
    Text: CDCLVD2108 www.ti.com SCAS905C – OCTOBER 2010 – REVISED DECEMBER 2010 Dual 1:8 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2108 FEATURES 1 • • • • • • • • • • • • Dual 1:8 Differential Buffer Low Additive Jitter <300 fs RMS in


    Original     		PDF CDCLVD2108 SCAS905C EIA/TIA-644A 48-Pin

    QFN-48 LAND PATTERN

    Abstract: No abstract text available
    Text: CDCLVP2108 SCAS878B – MAY 2009 – REVISED AUGUST 2011 www.ti.com 16 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP2108 FEATURES DESCRIPTION • • • The CDCLVP2108 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL


    Original     		PDF CDCLVP2108 SCAS878B 10-kHz 20-MHz QFN-48 QFN-48 LAND PATTERN

    Untitled

    Abstract: No abstract text available
    Text: CDCLVP1216 SCAS877C – MAY 2009 – REVISED AUGUST 2011 www.ti.com 16 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP1216 FEATURES DESCRIPTION • • • The CDCLVP1216 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL


    Original     		PDF CDCLVP1216 SCAS877C CDCLVP1216

    L510B

    Abstract: l815 l73a L61A L713 L-612 L814 l812 L313A AC105
    Text: Application Note AC105 Designing High-Speed ATM Switch Fabrics by Using Actel FPGAs The recent upsurge of interest in Asynchronous Transfer Mode ATM is based on the recognition that it represents a new level of both speed and simplification in telecommunication networks. The most significant


    Original     		PDF AC105 OUTP11 OUTP10 OUTP12 PADOUTP13 PADOUTP14 PADOUTP15 L510B l815 l73a L61A L713 L-612 L814 l812 L313A AC105

    Untitled

    Abstract: No abstract text available
    Text: Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CDCLVP1216 SCAS877D – MAY 2009 – REVISED JUNE 2014 CDCLVP1216 16 LVPECL Output, High-Performance Clock Buffer 1 Features 3 Description • • • The CDCLVP1216 is a highly versatile, low additive


    Original     		PDF CDCLVP1216 SCAS877D CDCLVP1216

    CDCLVP1216

    Abstract: CDCLVP1216RGZR CDCLVP1216RGZT QFN-48
    Text: CDCLVP1216 www.ti.com SCAS877B – MAY 2009 – REVISED MAY 2010 16 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP1216 FEATURES DESCRIPTION • • • The CDCLVP1216 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL


    Original     		PDF CDCLVP1216 SCAS877B CDCLVP1216 CDCLVP1216RGZR CDCLVP1216RGZT QFN-48

    Untitled

    Abstract: No abstract text available
    Text: CDCLVD1216 www.ti.com SCAS900B – OCTOBER 2010 – REVISED JANUARY 2011 2:16 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1216 FEATURES 1 • • • • • • • • • • • • 2:16 Differential Buffer Low Additive Jitter: <300 fs RMS in


    Original     		PDF CDCLVD1216 SCAS900B EIA/TIA-644A 48-Pin CDCLVD1216

    Untitled

    Abstract: No abstract text available
    Text: CDCLVD1216 www.ti.com SCAS900B – OCTOBER 2010 – REVISED JANUARY 2011 2:16 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1216 FEATURES 1 • • • • • • • • • • • • 2:16 Differential Buffer Low Additive Jitter: <300 fs RMS in


    Original     		PDF CDCLVD1216 SCAS900B EIA/TIA-644A 48-Pin CDCLVD1216

    QFN-48 LAND PATTERN

    Abstract: No abstract text available
    Text: CDCLVP2108 www.ti.com . SCAS878A – MAY 2009 – REVISED JULY 2009 16 LVPECL Output, High-Performance Clock Buffer


    Original     		PDF CDCLVP2108 SCAS878A CDCLVP2108 QFN-48 LAND PATTERN

    L510B

    Abstract: L17B AL211 L713
    Text: Appl i cat i on N ot e Designing High-Speed ATM Switch Fabrics by Using Actel FPGAs The recent upsurge of interest in Asynchronous Transfer Mode ATM is based on the recognition that it represents a new level of both speed and simplification in telecommunication networks. The most significant


    Original     		PDF OUTP12 PADOUTP13 OUTP10 PADOUTP14 PADOUTP15 OUTP11 L510B L17B AL211 L713

    R991

    Abstract: OUTP12
    Text: User's Guide SCAU029 – May 2009 Low Additive Phase Noise Clock Buffer Evaluation Board Figure 1. CDCLVP1216 Evaluation Board Features: • Easy-to-use evaluation board to fan out low phase noise clocks • Easy device setup • Fast configuration • Control pins configurable through jumpers


    Original     		PDF SCAU029 CDCLVP1216 CDCLVP1216EVM R991 OUTP12

    Untitled

    Abstract: No abstract text available
    Text: CDCLVP2108 SCAS878B – MAY 2009 – REVISED AUGUST 2011 www.ti.com 16 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP2108 FEATURES DESCRIPTION • • • The CDCLVP2108 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL


    Original     		PDF CDCLVP2108 SCAS878B 10-kHz 20-MHz QFN-48