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    OF 16 PIN IC M74HC1 Search Results

    OF 16 PIN IC M74HC1 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74HC4053FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SPDT(1:2)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T125FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T126FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation
    74HC4051FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SP8T(1:8)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL1G07FU Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Non-Inverter Buffer (Open Drain), USV, -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation

    OF 16 PIN IC M74HC1 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    54HC133

    Abstract: M74HC133B1
    Text: ^ t7 M54HC133 M74HC133 SCS-THOMSON m 13 INPUT NANDGATE HIGHSPEED tpD = 13 ns TYP. at Vcc = 5 V LOW POWER DISSIPATION Ice = 1 |iA (MAX.) at Ta = 25" C HIGH NOISE IMMUNITY V nih = V nil = 28 % Vcc (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OutpuT IMPEDANCE


    OCR Scan     		PDF 54HC133 74HC133 54/74LS133 54HC133F1R M74HC133B1 74HC133C1R M54/74HC133 13-INPUT

    74hc148a

    Abstract: 74HC148B1 74hc148b M74HC148B1R 74HC148M 74ls148 octal to binary encoder
    Text: r z 7 SCS-THOM SON ^7# M54HC148 M74HC148 l*i» L i T [M D g S 8 TO 3 LINE PRIORITY ENCODER • HIGHSPEED tpD = 15 ns (TYP. AT Vcc = 5 V . LOW POWER DISSIPATION Icc = 4 |iA (MAX.) AT Ta = 25 °C ■ HIGH NOISE IMMUNITY V nih = V nil = 28 % V c c (MIN.) ■ OUTPUT DRIVE CAPABILITY


    OCR Scan     		PDF M54HC148 M74HC148 54/74LS148 M54/74HC148 74HC148 74hc148a 74HC148B1 74hc148b M74HC148B1R 74HC148M 74ls148 octal to binary encoder

    74MC157

    Abstract: C5 74LS157 circuit diagram
    Text: £ Z T S G S -T H O M S O N ^7# M54HC157/158 M74HC157/158 HC157 QUAD 2 CHANNEL MULTIPLEXER HC158 QUAD 2 CHANNEL MULTIPLEXER INV. HIGH SPEED tPD = 10 ns (TYP.) AT Vcc = 5 V LOW POWER DISSIPATION Icc = 4 jiA (MAX.) AT Ta = 25 °C HIGH NOISE IMMUNITY V n ih = V n il = 28 % Vcc (MIN.)


    OCR Scan     		PDF M54HC157/158 M74HC157/158 HC157 HC158 54/74LS157/158 74MC157 C5 74LS157 circuit diagram

    74HC19

    Abstract: No abstract text available
    Text: r z 7 S C S -T H O M S O N ÎÎ5 Î Î Î S 3 S S ü * M iy iO T « S M74HC195 8 BIT PIPO SHIFT REGISTEF • HIGHSPEED tpD = 13 ns TYP. at V cc = 5 V ■ LOW POWER DISSIPATION Icc = 4 nA (MAX.) at Ta = 25 °C 6 V ■ HIGH NOISE IMMUNITY Vnih = V n il = 28 % V cc (MIN.)


    OCR Scan     		PDF M74HC195 54/74LS195 195F1R 195B1R M54/74HC 74HC195 74HC19

    74HC173

    Abstract: No abstract text available
    Text: £ t/ M 54HC173 M74HC173 SGS-THOMSON M QUAD D-TYPE REGISTER 3-STATE HIGHSPEED fMAX = 73 MHz (TYP.) at Vcc = 5 V LOW POWER DISSIPATION Ice = 4 |iA (MAX.) at Ta = 25 °C HIGH NOISE IMMUNITY V nih = Vnil = 28 % Vcc (MIN.) OUTPUT DRIVE CAPABILITY 15 LSTTLLOADS


    OCR Scan     		PDF 54HC173 M74HC173 54/74LS M54HC173F1 74HC173M 74HC173B1R 74HC173C1R 74HC173

    74LS131

    Abstract: 74HC131
    Text: S G S -T H O M S O N i*[R } i[L iM ô *S M54HC131 M74HC131 3 TO 8 LINE DECODER/LATCH • HIGHSPEED tpD = 22 ns (TYP. AT Vcc = 5 V . LOW POWER DISSIPATION Ice = 4 mA (MAX.) at Ta = 25 ‘C ■ HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) ■ OUTPUT DRIVE CAPABILITY


    OCR Scan     		PDF M54HC1 M74HC131 131C1R 54/74LS131 131F1R M54/74HC131 M54/M74HC131 74LS131 74HC131

    alu 181

    Abstract: M54HC182 M74HC181 M74HC182 M54/74HC181
    Text: HS-CMOS M54HC181 M74HC181 INTEGRATED CIRCUITS ARTHMETIC LOGIC UNIT/FUNCTION GENERATOR DESCRIPTION The M 54/74HC 181 is a high speed CM O S AR I­ THMETIC LOGIC UNIT/FUNCTION GENERATOR fabricated in silicon gate C 2MOS technology. It has th e same high speed perform ance of LSTTL


    OCR Scan     		PDF M54HC181 M74HC181 M54/74HC181 54/74LS181 alu 181 M54HC182 M74HC181 M74HC182

    M74HC109

    Abstract: 54HC 74HC M54HC109 74LS109
    Text: H S -C M O S INTEGRATED CIRCUITS 7 n M54HC109 4 f' M74HC109 P R E L IM IN A R Y D A T A DUAL J-K FLIP FLOP WITH PRESET AND CLEAR DESCRIPTION T h e M 5 4 /7 4 H C 1 0 9 is a hig h s p e e d C M O S D U A L J-K F L IP F L O P W IT H P R E S E T A N D C L E A R


    OCR Scan     		PDF M54HC109 M74HC109 M54/74HC109 M74HC109 54HC 74HC M54HC109 74LS109

    M74HC175

    Abstract: No abstract text available
    Text: / Z 7 SGS-THOMSON [RÆO gMMO¥M«S M54HC1 75 M74HC175 QUAD D-TYPE FLIP-FLOP WITH CLEAR HIGH SPEED tPD = 13 ns (TYP. AT Vcc = 5 V LOW POWER DISSIPATION Ice = 4 nA (MAX.) AT Ta = 25 °C HIGH NOISE IMMUNITY V nih = V nil = 28 % V cc (MIN.) OUTPUT DRIVE CAPABILITY


    OCR Scan     		PDF M54HC1 M74HC175 175F1R 175B1R M74HC175C1 54/74LS175 M54/74HC175 M74HC175

    74HC139b1

    Abstract: 74HC139B
    Text: r z 7 SCS-THOMSON Ä IM [*œ [L g O T @ res M54HC139 M74HC139 DUAL 2 TO 4 DECODER/DEMULTIPLEXER H IG H SP EE D tpD = 12 ns TYP. A T Vcc = 5 V LOW POWER DISSIPATION Ice = 4 nA (MAX.) AT T a = 25 "C HIGH NOISE IMMUNITY V nih = V nil = 28 % Vcc (MIN.) OUTPUT DRIVE CAPABILITY


    OCR Scan     		PDF M54HC139 M74HC139 54/74LS139 54HC139F1R M74HC1 74HC139B1R M54/74HC139 74HC139b1 74HC139B

    Untitled

    Abstract: No abstract text available
    Text: 5bE D • 7 ^ 2 3 7 0 0 3 ^ 7 M4M ■ SGTH M54HC166 M74HC166 SCS-THOMSON HLUraBSUimiÊi S 6 S-THOHSON 7 1-Lt -C>cl - 0 5 8 BIT PISO SHIFT REGISTER ■ HIGH SPEED *MAX = 50 MHz (TYP. at VCc = 5V ■ LOW POWER DISSIPATION |c c = 4 fJK (MAX.) at TA = 25°C ■ HIGH NOISE IMMUNITY


    OCR Scan     		PDF M54HC166 M74HC166 M54HC166 M74HC166 M54/74HC166 M54/74H

    74HC174

    Abstract: M74HC174B1N M74HC174
    Text: / S T SGS-THOM SON ^7# M » m ig T rM l g S M54HC174 M74HC174 HEX D-TYPE FLIP-FLOP WITH CLEAR • HIGH SPEED fMAX = 48 MHz (TYP. at VGc = 5V ■ LOW POWER DISSIPATION IC C = 4 fJK (MAX.) at Ta = 25°C i ■ HIGH NOISE IMMUNITY VNIH = V nil = 28% VCc (MIN.)


    OCR Scan     		PDF M54HC174 M74HC174 54/74LS174 M74HC174 M54/74HC174 M54/74HC174 74HC174 M74HC174B1N

    Untitled

    Abstract: No abstract text available
    Text: MITSUBISHI HIGH SPEED CMOS M74HC113P/FP/DP DUAL I -K F L IP -F L O P WITH S E T DESCRIPTION T he M 7 4 H C 1 1 3 is a sem ico n d u cto r integrated circu it co n ­ PIN CON FIGURATIO N TOP VIEW sistin g of of tw o n e g a tiv e -e d g e trig g ered J - K flip flops with


    OCR Scan     		PDF M74HC113P/FP/DP 14P2P G--06

    M74HC164

    Abstract: No abstract text available
    Text: SGS-THOMSON «¡R 3miOT iO gS M54HC164 M74HC164 8 BIT SIPO SHIFT REGISTER • HIGH SPEED tPD = 15 ns (TYP. AT Vcc = 5 V ■ LOW POWER DISSIPATION Icc = 4 (iA (MAX.) AT Ta = 25 °C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■ BALANCED PROPAGATION DELAYS


    OCR Scan     		PDF M54HC164 M74HC164 54/74LS164 M54HC164F1R M74HC164M1R M74HC164B1R M74HC164C1R M54/74HC164 DD54b3b M54/M74HC164 M74HC164

    M74HC133

    Abstract: No abstract text available
    Text: M54HC133 M74HC133 SGS-THOMSON * 5 7 ILO 13 INPUT NAND GATE HIGH SPEED tpD = 13 ns TYP. at Vcc = 5 V LOW POWER DISSIPATION Ice = 1 HA (MAX.) at Ta = 25* C HIGH NOISE IMMUNITY V nih = V nil = 28 % Vcc (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OutpuT IMPEDANCE


    OCR Scan     		PDF M54HC133 M74HC133 54/74LS133 M54HC133F1 74HC133M 74HC133B1R 74HC133C1R M54/74HC133 13-INÂ S-10275 M74HC133

    IC 74HC194

    Abstract: 74HC194 equivalent IC 74LS194 IC - 74hc194 74hc194 74LS194 internal circuit diagram
    Text: 7 SCS-THOMSON ^ 7 # » IÜ D » lllL i g ir[» H O (g i M54HC194 M74HC194 4 BIT PIPO SHIFT REGISTER • HIGH SPEED tPD = 13 ns (TYP. at VCc = 5V ■ LOW POWER DISSIPATION ICC = 4 >iA (MAX.) at TA = 2 5 °C ■ HIGH NOISE IMMUNITY V n IH = V n il = 28% VCc (MIN).


    OCR Scan     		PDF M54HC194 M74HC194 54/74LS194 M54/74HC194 M54/74HC194 IC 74HC194 74HC194 equivalent IC 74LS194 IC - 74hc194 74hc194 74LS194 internal circuit diagram

    ST chn 624

    Abstract: chn 624
    Text: MITSUBISHI HIGH S P E E D CMOS M74HC175P/FP/DP QUADRUPLE D -TYPE F L IP -F L O P WITH COMMON C LO C K AND R E S E T DESCRIPTION PIN CO NFIGURATION TOP VIEW T he M 7 4 H C 1 7 5 is a sem ico nd u cto r integrated circuit co n ­ sistin g of four p o s itiv e -e d g e -trig g e re d D -type flip flops with


    OCR Scan     		PDF M74HC175P/FP/DP 14-PIN 16-PIN 20-PIN G--06 ST chn 624 chn 624

    Untitled

    Abstract: No abstract text available
    Text: SGS-THOMSON « ^ [IL IO T îs« ! M54HC153/253 M74HC153/253 HC153 DUAL 4 CHANNEL MULTIPLEXER HC253 DUAL 4 CHANNEL MULTIPLEXER 3 STATE OUTPUT • HIGH SPEED tPD = 12 FIS TYP. at Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 4 nA (MAX.) at T a = 25 'C ■ HIGH NOISE IMMUNITY


    OCR Scan     		PDF M54HC153/253 M74HC153/253 HC153 HC253 54/74LS153/253 M54/M74HC153 M54/M74HC253

    Untitled

    Abstract: No abstract text available
    Text: MITSUBISHI HIGH SPEED CMOS M74HC10P M74HC10DP T R IP L E 3 -IN P U T P O S IT IV E NAND GATE DESCRIPTION The M 74H C 10 is a sem iconductor integrated c ircu it con­ sisting of three 3-in put p o s itiv e -lo g ic NAND, PIN CONFIGURATION TOP VIEW usable as


    OCR Scan     		PDF M74HC10P M74HC10DP

    74hc107

    Abstract: M74HC107B1N
    Text: / = T M54HC107 M74HC107 S G S -T H O M S O N « [10 [ M S I g ^ ( ô i0(gS DUAL J-K FLIP FLOP WITH CLEAR • HIGH SPEED f MAX = 58 M Hz (TYP.) at VC C = 5V ■ LOW POW ER DISSIPATION lCc = 2 nA (MAX.) at TA = 25°C ■ HIGH NOISE IM M U NITY V n ih = V NIL = 2 8 % VCC (MIN.)


    OCR Scan     		PDF M54HC107 M74HC107 54/74LS107 M74HC107 M54/74HC107 74hc107 M74HC107B1N

    74ls131

    Abstract: 74HC131
    Text: M54HC131 M74HC131 SGS-THOMSON 3 TO 8 LINE DECODER/LATCH • LOW POWER DISSIPATION |CC = 4 ¡A MAX. at Ta = 25°C ■ HIGH NOISE IMMUNITY VNIH = VN|L = 28% VCC (MIN.) ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■ SYMMETRICAL OUTPUT IMPEDANCE Mo h ! = lOL - 4 mA (MIN.)


    OCR Scan     		PDF M54HC131 M74HC131 54/74LS131 M54/74HC131 M54/74HC131 74ls131 74HC131

    74HC166

    Abstract: 54HC 74HC M54HC166 M74HC166 FZJ 125
    Text: M54HC166 M74HC166 SGS-THOMSON > 7 # . IM H M IIU llE M iiO IK g g 8 BIT PISO SHIFT REGISTER H IG H S P E E D fMAX = 50 M H z T Y P a t V CC = 5 V LO W P O W E R D IS S IP A T IO N Iq q = 4 fiA (M A X .) at T /\ = 2 5 ° C H IG H N O IS E IM M U N IT Y V N|H = V N il = 280/0 V CC (M IN .)


    OCR Scan     		PDF M54HC166 M74HC166 54/74LS166 M54/74HC166 M54/74HC166 74HC166 54HC 74HC M74HC166 FZJ 125

    pin configuration 74LS10

    Abstract: M74HC10P 4000B 74LS10 M74HC10 M74HC10DP of IC 74ls10 CMOS 74LS10 logic diagram of IC 74ls10 74LS10 mitsubishi
    Text: M IT S U B IS H I HIGH S P E E D C M O S M74HC10P M74HC10DP T R IP L E 3 -IN P U T P O S IT IV E NAND G A TE DESCRIPTION The M 74H C 10 is a sem iconductor integrated circu it con­ sisting of three 3-input p o sitive-lo gic PIN CONFIGURATION TOP VIEW NAND, usable as


    OCR Scan     		PDF M74HC10P M74HC10DP M74HC10 pin configuration 74LS10 4000B 74LS10 M74HC10DP of IC 74ls10 CMOS 74LS10 logic diagram of IC 74ls10 74LS10 mitsubishi

    74HC137

    Abstract: 54HC 74HC HC137 M54HC137 M74HC137
    Text: H S -C M O S ” INTEGRATED CIRCUITS / 1 1rf M54HC137 M74HC137 7 3 TO 8 LINE DECODER/LATCH INVERTING DESCRIPTION The M 54/74HC137 is a high speed CM OS 3 TO 8 LINE DECODER/LATCH (INVERTING) fabricated in silicon gate C2MOS technology. It has the same high speed perform ance of LSTTL com bined with


    OCR Scan     		PDF M54HC137 M54/74HC137 74HC137 54HC 74HC HC137 M54HC137 M74HC137