OC-24
Abstract: S3056 S3063 S3064 STM-16 STS-48
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-48 DIFFERENTIAL 1:16 RECEIVER BiCMOS LVPECL OC-12 CLOCKDIFFERENTIAL GENERATOR 1:16 SONET/SDH/ATM OC-48 TRANSMITTER ANDRECEIVER RECEIVER FEATURES S3064 S3064 S3064 GENERAL DESCRIPTION • Micro-power Bipolar technology
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OC-48
OC-12
S3064
OC-48)
16-bit
S3064
OC-48
OC-24
S3056
S3063
STM-16
STS-48
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S3042
Abstract: S3045 STS-48 S3040 S3041
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-48 8:1 TRANSMITTER BiCMOS LVPECL OC-12 CLOCK8:1 GENERATOR SONET/SDH/ATM OC-48 TRANSMITTER TRANSMITTER AND RECEIVER FEATURES GENERAL DESCRIPTION • Micro-power Bipolar technology • Complies with Bellcore and ITU-T
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OC-48
OC-12
OC-48)
S3041
S3042
S3045
STS-48
S3040
S3041
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Untitled
Abstract: No abstract text available
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-48 16:1 TRANSMITTER BiCMOS LVPECL OC-12 CLOCK16:1 GENERATOR SONET/SDH/ATM OC-48 TRANSMITTER TRANSMITTER AND RECEIVER GENERAL DESCRIPTION FEATURES • Micro-power Bipolar supply • Complies with Bellcore, and ITU-T
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OC-48
OC-12
S3043
S3043
OC-48)
16-bit
OC-48
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lsd 0007
Abstract: DW00
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-48 8:1 TRANSMITTER BiCMOS LVPECL OC-12 CLOCK8:1 GENERATOR SONET/SDH/ATM OC-48 TRANSMITTER TRANSMITTER AND RECEIVER FEATURES GENERAL DESCRIPTION • Micro-power Bipolar technology • Complies with Bellcore and ITU-T
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PDF
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OC-48
OC-12
S3041
S3041
OC-48)
OC-48
lsd 0007
DW00
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Untitled
Abstract: No abstract text available
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-48 16:1 TRANSMITTER BiCMOS LVPECL OC-12 CLOCK16:1 GENERATOR SONET/SDH/ATM OC-48 TRANSMITTER TRANSMITTER AND RECEIVER GENERAL DESCRIPTION FEATURES • Micro-power Bipolar supply • Complies with Bellcore, and ITU-T
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OC-48
OC-12
S3043
S3043
OC-48)
16-bit
OC-48
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OC-24
Abstract: S3040 S3043 S3044 STM-16 STS-48
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-48 16:1 TRANSMITTER BiCMOS LVPECL OC-12 CLOCK16:1 GENERATOR SONET/SDH/ATM OC-48 TRANSMITTER TRANSMITTER AND RECEIVER GENERAL DESCRIPTION FEATURES • Micro-power Bipolar supply • Complies with Bellcore, and ITU-T
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Original
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PDF
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OC-48
OC-12
OC-48)
16-bit
S3043
OC-48
OC-24
S3040
S3044
STM-16
STS-48
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Untitled
Abstract: No abstract text available
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-48 8:1 TRANSMITTER BiCMOS LVPECL OC-12 CLOCK8:1 GENERATOR SONET/SDH/ATM OC-48 TRANSMITTER TRANSMITTER AND RECEIVER FEATURES GENERAL DESCRIPTION • Micro-power Bipolar technology • Complies with Bellcore and ITU-T
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OC-48
OC-12
S3041
S3041
OC-48)
OC-48
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three phase sequence detector
Abstract: S3044 S3083 STM-16 STS-48 OC-24 S3040 AMCC qt
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-48 16:1 TRANSMITTER BiCMOS LVPECL OC-12 CLOCK16:1 GENERATOR SONET/SDH/ATM OC-48 TRANSMITTER TRANSMITTER AND RECEIVER S3083 S3083 S3083 GENERAL DESCRIPTION FEATURES • Micro-power Bipolar supply • Complies with Bellcore and ITU-T
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OC-48
OC-12
S3083
OC-48)
16-bit
S3083
three phase sequence detector
S3044
STM-16
STS-48
OC-24
S3040
AMCC qt
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Untitled
Abstract: No abstract text available
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-48 1:8 RECEIVER BiCMOS LVPECL OC-12 CLOCK1:8 GENERATOR SONET/SDH/ATM OC-48 RECEIVER AND RECEIVER TRANSMITTER FEATURES GENERAL DESCRIPTION • Micro-power Bipolar technology • Complies with ANSI, Bellcore, and ITU-T
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OC-48
OC-12
S3042
S3042
OC-48)
OC-48
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S3040
Abstract: S3041 S3042 S3045 STS-48
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-48 1:8 RECEIVER BiCMOS LVPECL OC-12 CLOCK1:8 GENERATOR SONET/SDH/ATM OC-48 RECEIVER AND RECEIVER TRANSMITTER FEATURES GENERAL DESCRIPTION • Micro-power Bipolar technology • Complies with Bellcore and ITU-T specifications
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OC-48
OC-12
OC-48)
S3042
OC-48
S3040
S3041
S3045
STS-48
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Untitled
Abstract: No abstract text available
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-48 1:16 RECEIVER BiCMOS LVPECL OC-12 CLOCK1:16 GENERATOR SONET/SDH/ATM OC-48 RECEIVER AND RECEIVER TRANSMITTER S3044 S3044 S3044 GENERAL DESCRIPTION FEATURES • Micro-power Bipolar technology • Complies with Bellcore and ITU-T
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OC-48
OC-12
S3044
S3044
OC-48)
16-bit
OC-48
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S3040
Abstract: S3043 S3044 STM-16 STS-48
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-48 1:16 RECEIVER BiCMOS LVPECL OC-12 CLOCK1:16 GENERATOR SONET/SDH/ATM OC-48 RECEIVER AND RECEIVER TRANSMITTER S3044 S3044 S3044 GENERAL DESCRIPTION FEATURES • Micro-power Bipolar technology • Complies with Bellcore and ITU-T
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OC-48
OC-12
S3044
OC-48)
16-bit
S3044
OC-48
S3040
S3043
STM-16
STS-48
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Untitled
Abstract: No abstract text available
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-48 1:16 RECEIVER BiCMOS LVPECL OC-12 CLOCK1:16 GENERATOR SONET/SDH/ATM OC-48 RECEIVER AND RECEIVER TRANSMITTER S3044 S3044 S3044 GENERAL DESCRIPTION FEATURES • Micro-power Bipolar technology • Complies with Bellcore and ITU-T
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PDF
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OC-48
OC-12
S3044
S3044
OC-48)
16-bit
OC-48
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Untitled
Abstract: No abstract text available
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-48 1:16 RECEIVER BiCMOS LVPECL OC-12 CLOCK1:16 GENERATOR SONET/SDH/ATM OC-48 RECEIVER AND RECEIVER TRANSMITTER S3044 S3044 S3044 GENERAL DESCRIPTION FEATURES • Micro-power Bipolar technology • Complies with Bellcore and ITU-T
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OC-48
OC-12
S3044
S3044
OC-48)
16-bit
OC-48
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ICS894D115I-04
Abstract: led clock circuit diagram ICS894D115I-01 ICS894D115AGI-04 ICS894D115I
Text: ICS894D115I-04 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-04 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or
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ICS894D115I-04
OC-12/STM-4
ICS894D115I-04
OC-12/STS-12)
led clock circuit diagram
ICS894D115I-01
ICS894D115AGI-04
ICS894D115I
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Untitled
Abstract: No abstract text available
Text: ICS894D115I-04 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-04 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or
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ICS894D115I-04
OC-12/STM-4
ICS894D115I-04
OC-12/STS-12)
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OC3 Tube
Abstract: C813C Nippon capacitors
Text: PRELIMINARY ICS894D115I-01 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-01 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or
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OC-12/STM-4
ICS894D115I-01
OC-12/STS-12)
08MHz
52MHz)
44MHz
ICS894D115I
EPAD441764
OC3 Tube
C813C
Nippon capacitors
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Untitled
Abstract: No abstract text available
Text: ICS894D115I-01 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-01 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or
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ICS894D115I-01
OC-12/STM-4
ICS894D115I-01
OC-12/STS-12)
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GD16592A
Abstract: GD16591A
Text: STM-4/STM-1/E4 3.3 V Multifunction Transmitter and Receiver GD16591A/GD16592A Preliminary General Description Features The GD16591A and GD16592A is a front-end transmitter/receiver chip set designed for multiple line interfaces: u STM-4 / OC-12 u STM-1 / OC-3
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GD16591A/GD16592A
GD16591A
GD16592A
OC-12
DK-2740
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10gd1
Abstract: GD16592A GD16591A PFC 1.5kw GD16591A-48BA PFC 50w schematic SON-5 E4 dsel12
Text: STM-4/STM-1/E4 3.3 V Multifunction Transmitter and Receiver GD16591A/GD16592A an Intel company General Description Features The GD16591A and GD16592A is a front-end transmitter/receiver chip set designed for multiple line interfaces: u STM-4 / OC-12 u STM-1 / OC-3
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GD16591A/GD16592A
GD16591A
GD16592A
OC-12
en-/de740
10gd1
PFC 1.5kw
GD16591A-48BA
PFC 50w schematic
SON-5 E4
dsel12
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2 way active crossover circuit diagram
Abstract: VCO 1.4 GHz STM-16 STS-48 OC-24 S3056 S3063 S3064 STS24
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-48 DIFFERENTIAL 16:1 TRANSMITTER SONET/SDH/ATM OC-48 DIFFERENTIAL 16:1 TRANSMITTER S3063 S3063 GENERAL DESCRIPTION FEATURES • Micro-power Bipolar supply • Complies with Bellcore, and ITU-T specifications • On-chip high-frequency PLL for clock
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OC-48
S3063
OC-48)
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S3063
2 way active crossover circuit diagram
VCO 1.4 GHz
STM-16
STS-48
OC-24
S3056
S3064
STS24
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GD16591-48BA
Abstract: 10gd1 gd16591
Text: STM-4/STM-1/E4 3.3 V Multifunction Transmitter and Receiver GD16591/GD16592 Preliminary General Description Features The GD16591 and GD16592 is a frontend transmitter/receiver chip set designed for multiple line interfaces: u STM-4 / OC-12 u STM-1 / OC-3 u PDH E4
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GD16591/GD16592
GD16591
GD16592
OC-12
GD16591/592
DK-2740
GD16591-48BA
10gd1
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SDM4123-XC
Abstract: SABRE 408 S3011 CMI encoder OC-24 S3015 S3016 STM-16 STS-48 MCL RMS-2
Text: DEVICE SPECIFICATION E4/STM-1/OC-3 ATM INTERFACE CIRCUITS S3015/S3016 E4/STM-1/OC-3 ATM INTERFACE CIRCUITS S3015/S3016 GENERAL DESCRIPTION FEATURES • Complies with ANSI, Bellcore, and ITU-T specifications • On-chip high-frequency PLL for clock generation and clock recovery
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S3015/S3016
SDM4123-XC
SABRE 408
S3011
CMI encoder
OC-24
S3015
S3016
STM-16
STS-48
MCL RMS-2
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GD16591A
Abstract: GD16592A GD16592A-48BA 10gd1
Text: STM-4/STM-1/E4 3.3 V Multifunction Transmitter and Receiver GD16591A/GD16592A an Intel company General Description Features The GD16591A and GD16592A is a front-end transmitter/receiver chip set designed for multiple line interfaces: u STM-4 / OC-12 u STM-1 / OC-3
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GD16591A/GD16592A
GD16591A
GD16592A
OC-12
en-/de740
GD16592A-48BA
10gd1
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