67164
Abstract: 0E12 UT67164 SRAM flatpack
Text: Standard Products UT67164 Radiation-Hardened 8K x 8 SRAM - SEU Hard Data Sheet December 1999 FEATURES q 55ns maximum address access time, single-event upset less than 1.0E-10 errors//bit day -55oC to 125+oC q Asynchronous operation for compatibility with industrystandard 8K x 8 SRAM
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UT67164
0E-10
-55oC
MIL-STD883
MIL-STD-883
28-pin
67164
0E12
SRAM flatpack
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tefr1
Abstract: 0E12 UT67164
Text: Standard Products UT67164 Radiation-Hardened 8K x 8 SRAM - SEU Hard Data Sheet December 1997 FEATURES q 55ns maximum address access time, single-event upset less than 1.0E-10 errors//bit day -55oC to 125+oC q Asynchronous operation for compatibility with industrystandard 8K x 8 SRAM
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UT67164
0E-10
-55oC
MIL-STD883
MIL-STD-883
SRAM-5-12-97-DS
tefr1
0E12
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Untitled
Abstract: No abstract text available
Text: Standard Products UT67164 Radiation-Hardened 8K x 8 SRAM - SEU Hard Data Sheet December 1997 FEATURES q 55ns maximum address access time, single-event upset less than 1.0E-10 errors//bit day -55oC to 125+oC q Asynchronous operation for compatibility with industrystandard 8K x 8 SRAM
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UT67164
0E-10
-55oC
MIL-STD883
MIL-STD-883
SRAM-5-12-97-DS
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Untitled
Abstract: No abstract text available
Text: 156 Mbps OPTICAL RECEIVER OD-J6503-HB01 FEATURES MAJOR PERFORMANCE • DESIGNED FOR SONET/SDH/ATM SYSTEMS • DATA RATE: 155.52 Mbps STM-1, OC-3 • REFLOW SOLDERABLE SMT PACKAGE • P-ECL SIGNAL LOGIC INTERFACE • COMPACT SIZE: 26 x 10 x 3 (mm) • ALARM FUNCTIONS:
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OD-J6503-HB01
24-Hour
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GR-253-CORE
Abstract: No abstract text available
Text: OD-J6501-0A01 OD-J6501-HB01 156 Mbps OPTICAL RECEIVER FEATURES MAJOR PERFORMANCE • DESIGNED FOR SONET/SDH/ATM SYSTEMS • DATA RATE: 155.52 Mbps STM-1, OC-3 • REFLOW SOLDERABLE SMD HOUSING • P-ECL SIGNAL LOGIC INTERFACE • COMPACT SIZE: 26 x 10 x 3 (mm)
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OD-J6501-0A01
OD-J6501-HB01
OD-J6501-0A01:
OD-J6501-HB01:
GR-253-Core
OD-J6501-HB01
Comp10
24-Hour
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0E12
Abstract: UT67164
Text: Standard Products UT67164 Radiation-Hardened 8K x 8 SRAM - SEU Hard Data Sheet January 2002 FEATURES q 55ns maximum address access time, single-event upset less than 1.0E-10 errors//bit day -55o C to 125+oC q Asynchronous operation for compatibility with industrystandard 8K x 8 SRAM
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UT67164
0E-10
MIL-STD883
MIL-STD-883
28-pin
0E12
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Untitled
Abstract: No abstract text available
Text: g THERMOCOUPLES: GENERAL INFORMATION Temperature measurement with thermocouples is based on measurement of electrical voltage. The output voltage emf of thermocouples, E, varies with the temperature in a predetermined fashion. The relationship between temperature t (oC) and emf E (mV) can be expressed by mathematical functions as follows:
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-270oC
1372oC:
t-126
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tca02
Abstract: AF-UNI-0010 0x513 concatenated and OC-3 and STM-1 ag20 tayio dfp 1016 TCA 105B CRC-16 CRC-32 GR-253-CORE
Text: 38 AM S/UNI -8x155 ASSP Telecom Standard Product Data Sheet Released da y, 14 Oc to S/UNI®-8x155 be r, 20 03 01 :0 4: PM5380 Data Sheet Released Issue No. 2: June 2002 lo ad ed by Am r Ma ns ou ro fS ilic on Ex pe rt Te cn ol og yI nc on Tu es SATURN® User Network Interface
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-8x155
-8x155
PM5380
8x155)
tca02
AF-UNI-0010
0x513
concatenated and OC-3 and STM-1
ag20 tayio
dfp 1016
TCA 105B
CRC-16
CRC-32
GR-253-CORE
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transistor C3866
Abstract: Zener PH SEC E13009 ups circuit schematic diagram 1000w E13007 2 E13007 C3866 power transistor texas ttl 74L505 Transistor C3246
Text: BID CΚΤ DOLLY L IST L OGO LIST SA F E TY & RELIA ΒL TY ΤΕΚ PIN SYSTE M DIGITA L IC's MEMORIES, MOS CMOS .EC L , TT L MICR OP R OC E SSOR SPE CIA L FUN CTION IC's DIGITAL l LINE AR K ARR AYS LIN E A R IC's (PUR CH ) ΤΕΚ-MADE IC's IC's INDEX (COL ORE D PGS)
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stk 412 -410
Abstract: IC stk 412 410 stk 142 150 C167SR-LM C166 C167 C167CR C167CR-16RM C167CR-4RM C167CR-LM
Text: U s er ’ s Ma n u al , V 3. 1 , M ar . 20 0 0 C167CR Derivatives 1 6- B i t S in gl e- C hi p M i cr oc o nt ro ll er Mi cro c on tr ol le rs N e v e r s t o p t h i n k i n g . Edition 2000-03 Published by Infineon Technologies AG, St.-Martin-Strasse 53,
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C167CR
D-81541
C167CR
stk 412 -410
IC stk 412 410
stk 142 150
C167SR-LM
C166
C167
C167CR-16RM
C167CR-4RM
C167CR-LM
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TC1796-L
Abstract: TC1796ED TC1796 user manual
Text: D oc u m e nt a t i o n A d d e nd u m , V 1 . 0 , N o v . 2 0 0 5 T C17 96 3 2 - B i t S i n g l e - C h i p M i c ro c o n t r o ll e r M i c r o c o n t r o l l e rs N e v e r s t o p t h i n k i n g . Edition 2005-11 Published by Infineon Technologies AG,
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LTCCTR63
0400H
05FFH
0600H
07FFH
TC1796-L
TC1796ED
TC1796 user manual
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Pulse generator wiring diagram
Abstract: EMV-PG01L EMV-PG01X EMV-PG01O pg01o incremental encoder AWG16 AWG18 12v generator diagram 3 PHASE MOTOR line wiring diagram
Text: 2007-04-12 A. Y EMV-PG01O Wiring 1 jumper 2.1 Outline Braking resistor optional Non-fuse breaker 5011647401-EM01 http://www.delta.com.tw/industrialautomation/ R NFB S EMV-PG01 Instruction Sheet T REV/STOP Multi-step 1 Factory setting Multi-step 2 Multi-step 3
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EMV-PG01O
5011647401-EM01
EMV-PG01
EMV-PG01X
25mm2
AWG16)
Pulse generator wiring diagram
EMV-PG01L
EMV-PG01X
EMV-PG01O
pg01o
incremental encoder
AWG16
AWG18
12v generator diagram
3 PHASE MOTOR line wiring diagram
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FB 3306
Abstract: 7200L 18504 845 motherboard circuit 7804 inverter 7805 ACT 845 motherboard BTL 8 236 CMOS 4060 cmos open collector
Text: Section 2 Functional Index Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Inverting/Noninverting Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 Buffers/Drivers and Bus Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
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Untitled
Abstract: No abstract text available
Text: Full Accurate 14/16 Bit Vout nanoDacTM, Buffered, 3V/5V, Sot 23 AD5040/AD5060 Preliminary Technical Data FEATURES Single 14/16-Bit DAC, 1 Lsb inl. Power-On-Reset to Zero Volts/Mid Scale Three Power-Down Functions Low Power Serial Interface with SchmittTriggered Inputs
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14/16-Bit
Sot23
AD5040/AD5060
AD5061
AD5040/AD5060.
PR04767-0-2/05
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OC-106 94V0 C
Abstract: olin 7025 CDA 194 Tamac4 eftec 7025 alloy lead frame sn 8400 Au Sn eutectic thermal conductivity Eftec 64t
Text: 2 5 Physical Constants of IC Package Materials 1/16/97 3:41 PM CH05WIP.DOC INTEL CONFIDENTIAL until publication date 2 CHAPTER 5 PHYSICAL CONSTANTS OF IC PACKAGE MATERIALS The Table 5-1 through Table 5-5 list typical values for selected properties of materials used in
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CH05WIP
300oC
OC-106 94V0 C
olin 7025
CDA 194
Tamac4
eftec
7025 alloy lead frame
sn 8400
Au Sn eutectic
thermal conductivity
Eftec 64t
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AD5060BRJ-2REEL7
Abstract: No abstract text available
Text: Full Accurate 14/16 Bit Vout nanoDacTM, Buffered, 3V/5V, Sot 23 AD5040/AD5060 Preliminary Technical Data FEATURES Single 14/16-Bit DAC, 1 Lsb inl. Power-On-Reset to Zero Volts/Mid Scale Three Power-Down Functions Low Power Serial Interface with SchmittTriggered Inputs
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14/16-Bit
Sot23
AD5040/AD5060
AD5061
AD5040/AD5060.
PR04767-0-1/05
AD5060BRJ-2REEL7
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FB 3306
Abstract: pcf 817 CD4000 SERIES BOOK BR 8550 sn 16861 7 SEGMENT DISPLAY cd 4511 74 LS 00 Logic Gates pcf 9555 HC 40106 NXP 74LVC1G
Text: TM Technology for Innovators Logic Selection Guide 2007 2 ➔ Logic Selection Guide Texas Instruments Important Notice Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any
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oak technology oti 067
Abstract: oak oti-067 P2WKP
Text: DC SPECIFICATION ABSOLUTE MAXIMUM RATINGS Ambient Operating Temperature OC to +70C Storage Temperature -65 deg C to +150 deg C Supply Voltage to Ground Potential -0.5V to +7.0V Applied Input Voltage -0.5V to +7.0V Stresses above those listed may cause permanent damage to the device. These are
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-WE01
oak technology oti 067
oak oti-067
P2WKP
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pin diagram of mc68hc811e2
Abstract: 48-Pin DIP MC68HC811E2 1838 ir receiver 11E20 4800 FF adcb 27 MC68HC711 STK 5333 MC68S711E9 MC68HC11
Text: MC68HC11ERG/AD M68HC11E SERIES PROGRAMMING REFERENCE GUIDE M MOTOROLA Block Diagram PAI/OC 1 0C2/0C1 0C3/0C1 0C4/0C1 IC4/OC5/OC1 IC1 IC2 IC3 PA7/PAI/0C1 PA6/OC2/OC1 PA5/OC3/OC1 PA4/OC4/OC1 PA3/IC4/OC5/OC10 ) PA2/IC1 — > PA1/IC2— > PA0/IC3— >• PULSE ACCUMULATOR
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MC68HC11
M68HC11E
PB7/ADDR15*
PB6/ADDR14-PB5/ADDR13*
PB4/ADDR12*
PB3/ADDR11
-PB2/ADDR10*
pin diagram of mc68hc811e2
48-Pin DIP MC68HC811E2
1838 ir receiver
11E20
4800 FF
adcb 27
MC68HC711
STK 5333
MC68S711E9
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8713B
Abstract: T648 B1193 T646
Text: SN54HCT646. SN54HCT648, SN74HCT646, SN74HCT648 OC TAL BUS TRAN SC EIVERS AN D REGISTERS WITH 3 S TA TE OUTPUTS D 2 8 0 4 , M AR C H 1 9 8 4 -R E V IS E D SEPTEMBER 1 9 8 7 • Inputs are TTL-Voltage Compatible • Independent Registers lor A and B Buses •
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SN54HCT646.
SN54HCT648,
SN74HCT646,
SN74HCT648
300-mil
SN54H
8713B
T648
B1193
T646
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MIL-M-38510 301
Abstract: ax 3003 1N3064 TT 46 N 16 LOF 13003J
Text: r MIL-M-38510/331A 4 November 1985 _ s i p m s m r f n i -MIL-M-38510/33HUSAF 26 J u n e 1 9 7 8 SPECIFICATION military MI CR OC IRC UI TS, DIGITAL, 3 IPOLAR ^OW-POMER FLIP-FLOPS, CASCAOABLE, MONOLITHIC T h i s s p e c i f i c a t i o n is a p p r o v e d f o r us e by al 1
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MIL-M-38510/331A
MIL-M-38510/331
MIL-M-38510.
MIL-M-38510 301
ax 3003
1N3064
TT 46 N 16 LOF
13003J
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ic 8086
Abstract: 616P
Text: 71 A±0.3C B ± 0 .15 Specificotions: o o o o o o o o o o o o OOOOOOOOOOOOOO N o t e l: With m iddle b c r 18 - 6 4 P} ^ÎlTTTTTTTTTTT? I I. 2.5»±0.10 PO.3 [I 1F I A+0.3C 3 C ir c u its D W .A DIM.B 6 7.62 1016 5.08 OIV.C 10.16 DIU.D 7.62 6 1-4 16 7.6 2
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18-64P}
6-16P)
UL94V-0)
24-Oct
PC0001)
54rrim
2121-xxE
ic 8086
616P
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Untitled
Abstract: No abstract text available
Text: 10 39170 92.4 16 POSITION SHOWN NO. OR DIM. M A T E R IA L CIRCUITS "A" NUMBER 14 50.8 [2.00] 39170-1014 16 53.3 [2.10] 39170-1016 20 61.0 [2.40] 39170-1020 26 76.2 [3.00] 39170-1026 34 95.0 [5.74] 59170-1034 40 111.5 [4.59] 59170-1040 50 135.6 [5.34] 39170-1050
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SD-39170-005
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l1113
Abstract: No abstract text available
Text: F 10168 • F 10568 F10K VOLTAGE COMPENSATED ECL QUAD LATCH/GATED OUTPUTS DESCRIPTION - The F10168 and F10568 contains four D type latches with a Common Enable Ec . When E c is HIGH, outputs will follow the D inputs. Information is latched on the negative-going edge of E c Each latch output is combined with a separate gate control (Gn),
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F10168
F10568
l1113
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