CY7C1367A
Abstract: GVT71512C18 4947a SRAM controller
Text: CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 256K x 36/512K x 18 Synchronous Pipelined SRAM Features • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns • Fast clock speed: 225 MHz, 200 MHz, 166 MHz, and 150 MHz • Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
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Original
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CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
36/512K
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
CY7C1367A
GVT71512C18
4947a
SRAM controller
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PDF
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NS-346B
Abstract: 10KHZ NS-346A NS-346C NS-346D NS-346E 1MHz-1000MHz
Text: BROADBAND CALIBRATED NOISE STANDARDS 10KHZ TO 26.5GHZ DESCRIPTION BROADBAND CALIBRATED OUTPUT CHARACTERISTICS FOR USE WITH NOISE FIGURE M ETERS MODEL FREQUENCY NS-346A * 0.01-18 GHz NS-346B * 0.01-18 GHz NS-346C + 0.01-26.5 GHz NS-346D * 0.01-18 GHz NS-346E + 0.01-26.5 GHz
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Original
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10KHZ
NS-346A
NS-346B
NS-346C
NS-346D
NS-346E
5-18GHz
RFN/30-10
RFN/25L
RFN/25S
NS-346B
NS-346A
NS-346C
NS-346D
NS-346E
1MHz-1000MHz
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PDF
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CY7C1360A
Abstract: CY7C1362A 1362A
Text: CY7C1360A CY7C1362A 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
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Original
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CY7C1360A
CY7C1362A
36/512K
CY7C1360A
CY7C1362A
1362A
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PDF
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CY7C1360A
Abstract: CY7C1362A
Text: CY7C1360A CY7C1362A 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
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Original
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CY7C1360A
CY7C1362A
36/512K
CY7C1360A
CY7C1362A
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1360A CY7C1362A 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
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Original
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CY7C1360A
CY7C1362A
36/512K
CY7C1360A
CY7C1362A
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PDF
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28F128W18
Abstract: 28F320W18 28F640W18 intel DOC matrix 7x8
Text: 1.8 Volt Intel Wireless Flash Memory W18 28F320W18, 28F640W18, 28F128W18 Preliminary Datasheet Product Features Performance — 70 ns Asynchronous reads for 32 and 64 Mbit, 90 ns for 128 Mbit — 14 ns Clock to Data Output (tCHQV) — 20 ns Page Mode Read Speed
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Original
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28F320W18,
28F640W18,
28F128W18
128-Mbit
56-Ball
32-Mbit)
64-Mbit)
128-Mbit)
28F128W18
28F320W18
28F640W18
intel DOC
matrix 7x8
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PDF
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Untitled
Abstract: No abstract text available
Text: CYPRESS SEMICONDUCTOR Flash Erasable, Reprogrammable CMOS PAL Device DIP, LCC, and PLCC available — 7.5 ns commercial version 5 ns tco 5 ns t§ 7.5 ns tpo 133-MHz state machine — 10 ns military and industrial ver sions 6 ns tco 6 ns tg 10 ns tpo 110-MHz state machine
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OCR Scan
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133-MHz
110-MHz
15-ns
25-ns
28-Square
24-Lead
PALC22V10Dâ
PALC22V10D
24-Lead
300-Mil)
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PDF
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Untitled
Abstract: No abstract text available
Text: iw VITELIC V 53C 256 FAMILY HIG H PERFORMANCE, LOW POWER 2S 6K X 1 B IT FAST PAGE MODE CMOS D YN AM IC RAM f HIGH PERFORMANCE V53C256 70/70L 80/80L Max. RAS Access Time, tRAC 70 ns 80 ns 100 ns 120 ns Max. Column Address Access Time, tQAA 35 ns 40 ns 45 ns
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OCR Scan
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V53C256
70/70L
80/80L
V53C256L
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PDF
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Untitled
Abstract: No abstract text available
Text: ^ TTL Programmable Delay Modules Step Delay Max. Delay Output Rise Part No. ns ± ns ns ± ns time ns TTLPG301 TTLPG302 TTLPG303 TTLPG304 TTLPG305 TTLPG306 TTLPG307 TTLPG308 TTLPG309 TTLPG310 TTLPG315 TTLPG320 TTLPG325 TTLPG330 TTLPG335 TTLPG340 TTLPG345
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OCR Scan
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PDF
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Untitled
Abstract: No abstract text available
Text: iw“ VITELIC V53C1OOB FAMILY HIGH PERFORMANCE LOW POWER 1M X 1 BIT FAST PAGE MODE CMOS DYNAMIC RAM PRELIMINARY , 60/60L 70/70L 80/80L Max. RAS Access Time, tRAC 60 ns 70 ns 80 ns Max. Column Address Access Time, (tCAA) 30 ns 35 ns 40 ns Max. CAS Access Time, (tCAC)
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OCR Scan
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V53C1OOB
60/60L
70/70L
80/80L
V53C100B
V53C100BL
V53C100B-80
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PDF
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L-SIM-30-1
Abstract: No abstract text available
Text: SIEMENS 1 M X 8-Bit Dynamic RAM Module HYM 22100S-60/-70/-80 Advanced Information • 1 048 576 words by 8-bit organization • Fast access and cycle 60 ns access time 110 ns cycle time -60 70 ns access time 130 ns cycle time (-70 80 ns access time 150 ns cycle time (-80
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OCR Scan
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22100S-60/-70/-80
0235b05
5550b
L-SIM-30-1
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PDF
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V53C400
Abstract: PIN CONFIGURATION 7411 TTL 7411 ms1953
Text: I s V VITELIC V53C400 HIGH PERFORMANCE, LO W POWER 4M X 1 B IT FAST PAGE MODE CMOS DYNAMIC RAM PRELIMINARY 70/70L 80/80L 10/10L Max. RAS Access Time, tRAC 70 ns 80 ns 100 ns Max. Column Address Access Time, (tCAA) 35 ns 40 ns 50 ns Min. Fast Page Mode Cycle Time, ( t ^ )
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OCR Scan
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V53C400
70/70L
80/80L
10/10L
V53C400L
V53C400-10
V53C400L-0
PIN CONFIGURATION 7411
TTL 7411
ms1953
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PDF
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Untitled
Abstract: No abstract text available
Text: M i i V VITELIC V53C400 HIGH PERFORMANCE, LOW POWER 4M X 1 BIT FAST PAGE MODE CMOS DYNAMIC RAM PRELIMINARY 70/70L 80/80L 10/10L Max. RAS Access Time, tRAC 70 ns 80 ns 100 ns Max. Column Address Access Time, (tCAA) 35 ns 40 ns 50 ns Min. Fast Page Mode Cycle Time, (tpc)
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OCR Scan
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V53C400
70/70L
V53C400
80/80L
10/10L
V53C400L
V53C400-10
V53C400L
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PDF
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256KX4
Abstract: V53C104B V53C104 casco battery
Text: JVH VITEUC V53C104B HIGH PERFORMANCE, LO W POW ER 256K X 4 B IT FA S T PAGE MODE CMOS DYNAMIC RAM PRELIMINARY 60/60L 70/70L 80/80L Max. RAS Access Time, tp ^ 60 ns 70 ns 80 ns Max. Column Address Access Time, (tCAA) 30 ns 35 ns 40 ns Min. Fast Page Mode Cyde Time, (tp^)
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OCR Scan
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V53C104B
60/60L
70/70L
80/80L
V53C104BL
V53C104B-80
V53C104B-1
256KX4
V53C104
casco battery
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PDF
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Untitled
Abstract: No abstract text available
Text: if “ VITELIC V53C404 HIGH PERFORMANCE, LO W POWER 1 M X 4 B IT FAST PAGE MODE CMOS DYNAMIC RAM PRELIMINARY 70/70L 80/80L 10/10L Max. RAS Access Time, tRAC 70 ns 80 ns 100 ns Max. Column Address Access Time, (tCAA) 35 ns 4 0 ns 50 ns Min. Fast Page Mode Cycle Time, (tpç)
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OCR Scan
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V53C404
70/70L
V53C404
80/80L
10/10L
V53C404L
V53C404-10
V53C404L
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PDF
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Untitled
Abstract: No abstract text available
Text: M O S E L V TTE U C PRELIMINARY V52C8258 MULTIPORT VIDEO RAM WITH 256K X 8 DRAM AND 512 X 8 SAM HIGH PERFORM ANCE V 52C8258 60 70 80 Max. RAS Access Time, Irac 60 ns 70 ns 80 ns Max. CAS Access Time, (Icac) 15 ns 20 ns 25 ns Max. Column Address Access Time, (t^ )
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OCR Scan
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V52C8258
52C8258
V52C8258
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PDF
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Untitled
Abstract: No abstract text available
Text: PLDC18G8 I CYPRESS SEMICONDUCTOR • Fast — Commercial: tpo = 12 ns, tc o = 10 ns, t§ = 10 ns — Military/Industrial: tpD = 15 ns, t c o = 12 ns, t§ — 12 ns • Low power Generic architecture to replace stan dard logic functions including: 10H8, 1 2 H 6 ,1 4 H 4 ,16H 2,10L 8,12L 6,14L 4,
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OCR Scan
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PLDC18G8
disconnDC18G8Lâ
20-Lead
300-Mil)
PLDC18G8Lâ
C18G8-12W
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PDF
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palce22v10 programming guide
Abstract: No abstract text available
Text: PALCE22V10 CYPRESS Flash Erasable, Reprogrammable CMOS PAL Device Features 5 ns tpo 181-MHz state machine • Low power — 10 ns military and industrial versions 7 nstco — 90 mA max. commercial 10 ns 6 nsts 10 ns tpQ — 130 mA max. commercial (5 ns)
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OCR Scan
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181-MHz
PALCE22V10
110-MHz
15-ns
25-ns
24-Lead
300-Mil)
24-Lead
palce22v10 programming guide
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PDF
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256KX4
Abstract: V53C104B AA44A V53C104
Text: Mu ! *m — iw“ VITEUC V53C104B HIGH PERFORMANCE, LOW POWER 256K X 4 B IT FAST PAGE MODE CMOS DYNAMIC RAM PRELIMINARY 60/60L 70/70L 80/80L Max. RAS Access Time, tp ^ 60 ns 70 ns 80 ns Max. Column Address Access Time, (tCAA) 30 ns 35 ns 40 ns Min. Fast Page Mode Cyde Time, (tpç)
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OCR Scan
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V53C104B
60/60L
70/70L
80/80L
V53C104BL
200fiA
200jiA
200fiA
V53C104B-80
256KX4
AA44A
V53C104
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PDF
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Untitled
Abstract: No abstract text available
Text: VITEUC V53C100H UL TRA-HIGH PERFORMANCE LOW POWER 1MX1 BIT FAST PAGE MODE CMOS DYNAMIC RAM HIGH PERFORMANCE V53C100H ADVANCE INFORMA TION 45/45L 50/50L 55/55L 60/60L Max. RAS Access Time, 45 ns 50 ns 55 ns 60 ns Max. Column Address Access Time, tCAA 24 ns
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OCR Scan
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V53C100H
45/45L
50/50L
55/55L
60/60L
V53C100HL
31NrlSe^
C9145
A53-11
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PDF
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V53C104
Abstract: l04b 256KX4 V53C104B tnr dip mil std v53c104b80
Text: JVH VITEUC V53C104B HIGH PERFORMANCE, LO W POW ER 256K X 4 B IT FA S T PAGE MODE CMOS DYNAMIC RAM PRELIMINARY 6 0 /6 0 L 7 0 /7 0 L 8 0 /80L Max. RAS Access Time, t p ^ 60 ns 70 ns 80 ns Max. Column Address Access Time, (tCAA) 30 ns 35 ns 40 ns Min. Fast Page Mode Cyde Time, (tp^)
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OCR Scan
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V53C104B
60/60L
70/70L
80/80L
V53C104BL
V53C104B-80
V53C104B-1
V53C104
l04b
256KX4
tnr dip mil std
v53c104b80
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PDF
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Untitled
Abstract: No abstract text available
Text: An m im y V1TELIC V53C404 HIGH PERFORMANCE, LO W POWER 1 M X 4 B IT FAST PAGE MODE CMOS DYNAMIC RAM PRELIMINARY 7 0 /7 0 L 8 0 /8 0 L 1 0 /10L Max. RAS Access Time, tRAC 70 ns 80 ns 100 ns Max. Column Address Access Time, {tCAA) 35 ns 40 ns 50 ns Min. Fast Page Mode Cycle Time, ( t ^ )
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OCR Scan
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V53C404
70/70L
80/80L
10/10L
V53C404L
V53C404-10
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PDF
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HH2C
Abstract: No abstract text available
Text: An m im y V1TELIC V53C404 HIGH PERFORMANCE, LO W POWER 1 M X 4 B IT FAST PAGE MODE CMOS DYNAMIC RAM PRELIMINARY 7 0 /7 0 L 8 0 /8 0 L 1 0 /10L Max. RAS Access Time, tRAC 70 ns 80 ns 100 ns Max. Column Address Access Time, {tCAA) 35 ns 40 ns 50 ns Min. Fast Page Mode Cycle Time, ( t ^ )
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OCR Scan
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V53C404
70/70L
80/80L
10/10L
V53C404L
V53C404-10
HH2C
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PDF
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siemens capacitors
Abstract: E309
Text: SIEMENS 1 M X 8-Bit Dynamic RAM Module HYM 22100S-60/-70/-80 Advanced Information • 1 048 576 words by 8-bit organization • Fast access and cycle time 60 ns access time 110 ns cycle time -60 version 70 ns access time 130 ns cycle time (-70 version) 80 ns access time
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OCR Scan
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22100S-60/-70/-80
siemens capacitors
E309
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PDF
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