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    NAND GATE LAYOUT Search Results

    NAND GATE LAYOUT Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TLP5702H Toshiba Electronic Devices & Storage Corporation Photocoupler (Gate Driver Coupler), High-Topr / IGBT driver, 5000 Vrms, SO6L Visit Toshiba Electronic Devices & Storage Corporation
    TLP5705H Toshiba Electronic Devices & Storage Corporation Photocoupler (Gate Driver Coupler), High-Topr / IGBT driver, 5000 Vrms, SO6L Visit Toshiba Electronic Devices & Storage Corporation
    TB67H481FTG Toshiba Electronic Devices & Storage Corporation Stepping and Brushed Motor Driver /Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / IN input type / VQFN32 Visit Toshiba Electronic Devices & Storage Corporation
    GT30J110SRA Toshiba Electronic Devices & Storage Corporation IGBT, 1100 V, 60 A, Built-in Diodes, TO-3P(N) Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T125FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation

    NAND GATE LAYOUT Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: OBSOLETE 100304 www.ti.com SNOS120B – AUGUST 1998 – REVISED APRIL 2013 100304 Low Power Quint AND/NAND Gate Check for Samples: 100304 FEATURES DESCRIPTION • • • • The 100304 is monolithic quint AND/NAND gate. The Function output is the wire-NOR of all five AND gate


    Original     		SNOS120B PDF

    JESD30E

    Abstract: 74AUP1G00
    Text: 74AUP1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G00 is a single 2-input positive NAND gate with a


    Original     		74AUP1G00 74AUP1G00 DS35145 JESD30E PDF

    Untitled

    Abstract: No abstract text available
    Text: 74AUP1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G00 is a single 2-input positive NAND gate with a


    Original     		74AUP1G00 74AUP1G00 DS35145 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74AUP1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G00 is a single 2-input positive NAND gate with a


    Original     		74AUP1G00 74AUP1G00 DS35145 PDF

    NAND 74 SOT353

    Abstract: 74LVC1G00 A115-A
    Text: 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The 74LVC1G00 is a single 2-input positive NAND gate with Top View a standard totem pole output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The


    Original     		74LVC1G00 74LVC1G00 OT353 DS32196 NAND 74 SOT353 A115-A PDF

    A115-A

    Abstract: DFN1410 ds3221
    Text: 74LVCE1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments Top View The 74LVCE1G00 is a single 2-input positive NAND gate with a standard totem pole output. The device is designed for operation with a power supply range of 1.4V to 5.5V. A 1


    Original     		74LVCE1G00 74LVCE1G00 OT353 DS32210 A115-A DFN1410 ds3221 PDF

    74AHCT1G00

    Abstract: A115-A VM MARKING CODE SOT353
    Text: 74AHCT1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The 74AHCT1G00 is a single 2-input positive NAND gate Top View with a standard totem pole output. The device is designed for operation with a power supply range of 4.5V to 5.5V. The


    Original     		74AHCT1G00 74AHCT1G00 OT353 DS35179 A115-A VM MARKING CODE SOT353 PDF

    74LVC1G00

    Abstract: A115-A DFN1410 Single 2-Input AND GATE type name
    Text: 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments Top View The 74LVC1G00 is a single 2-input positive NAND gate with a standard totem pole output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The


    Original     		74LVC1G00 74LVC1G00 OT353 DS32196 A115-A DFN1410 Single 2-Input AND GATE type name PDF

    toshiba smd marking code transistor

    Abstract: No abstract text available
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview MC74LCX38 Low-Voltage CMOS Quad 2-Input NAND Gate, Open Drain With 5V-Tolerant Inputs The MC74LCX38 is a high performance, open drain quad 2–input NAND gate operating from a 2.7 to 3.6V supply. High impedance TTL


    Original     		MC74LCX38 MC74LCX38 BR1339 toshiba smd marking code transistor PDF

    Untitled

    Abstract: No abstract text available
    Text: 74AHCT1G00 SINGLE 2 INPUT POSITIVE NAND GATE Pin Assignments Description The 74AHCT1G00 is a single 2-input positive NAND gate Top View with a standard totem pole output. The device is designed for operation with a power supply range of 4.5V to 5.5V. The


    Original     		74AHCT1G00 74AHCT1G00 OT353 DS35179 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments Top View The 74LVC1G00 is a single 2-input positive NAND gate with a standard totem pole output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The


    Original     		74LVC1G00 74LVC1G00 OT353 DS32196 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments Top View The 74LVC1G00 is a single 2-input positive NAND gate with a standard push-pull output. The device is designed for A 1 operation with a power supply range of 1.65V to 5.5V. The


    Original     		74LVC1G00 74LVC1G00 OT353 DS32196 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74AHC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Pin Assignments Description The 74AHC1G00 is a single 2-input positive NAND gate with Top View a standard push-pull output. The device is designed for operation with a power supply range of 2.0 V to 5.5 V. The


    Original     		74AHC1G00 74AHC1G00 OT353 DS35169 PDF

    74AHC1G00

    Abstract: A115-A 74AHC1G00SE-7
    Text: 74AHC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The 74AHC1G00 is a single 2-input positive NAND gate with Top View a standard push-pull output. The device is designed for operation with a power supply range of 2.0 V to 5.5 V. The


    Original     		74AHC1G00 74AHC1G00 OT353 DS35169 A115-A 74AHC1G00SE-7 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The 74LVC1G00 is a single 2-input positive NAND gate with a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to


    Original     		74LVC1G00 74LVC1G00 DS32196 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVCE1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The 74LVCE1G00 is a single 2-input positive NAND gate with a standard totem pole output. The device is designed for operation with a power supply range of 1.4V to 5.5V. A 1 B 2 5 Vcc


    Original     		74LVCE1G00 74LVCE1G00 DS32210 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74AUP1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed ( Top View ) for low power and extended battery life in portable applications. ( Top View ) A 1 The 74AUP1G00 is a single 2-input positive NAND gate with a


    Original     		74AUP1G00 74AUP1G00 X2-DFN0808-4 OT353 DS35145 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments Top View ( Top View ) The 74LVC1G00 is a single 2-input positive NAND gate with A 1 a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The


    Original     		74LVC1G00 74LVC1G00 OT553 OT353 DS32196 PDF

    hef4093b

    Abstract: schmitt trigger application sheet HEF4093BC HEF4093BP
    Text: HEF4093B Quad 2-input NAND Schmitt trigger Rev. 8 — 21 November 2011 Product data sheet 1. General description The HEF4093B is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches at different points for positive-going and negative-going signals. The


    Original     		HEF4093B HEF4093B schmitt trigger application sheet HEF4093BC HEF4093BP PDF

    ic cmos 4014

    Abstract: 408000 144 p LQFP PACKAGE
    Text: Sea-of-Gate Type CMOS Gate Arrays CG51 Series Features High integration: Maximum 753,768 BCs on chip Technology: Silicon-gate, 3-layer metal wiring Base circuit (basic cell): 2-input NAND/2-input NOR gates Gate delay time: 210 ps (High-speed type 2-input NAND f/o=2 standard load)


    OCR Scan     		PDF

    D4011

    Abstract: 4011U
    Text: ¡3 HARRIS C D 4 0 1 1 U B T yp e s CMOS Quad 2-Input NAND Gate High-Voltage Types 20-Volt Rating m CD4011UBquad 2-input NAND gate provides the system designer with direct implementation o f the NAND func­ tion and supplements the existing fam ily of CMOS gates.


    OCR Scan     		20-Volt CD4011UBquad CD4011UB 14lead 14-lead D4011 4011U PDF

    Untitled

    Abstract: No abstract text available
    Text: ^ Tex a s In s t r u m e n t s CD4011UB Types Data sheet acquired from Harris S em iconductor S C H S 022 CMOS Quad 2-Input NAND Gate High-Voltage Types 20-Volt Rating • CD4011UB quad 2-input NAND gate provides the system designer with direct Implementation of the NAND func­


    OCR Scan     		CD4011UB 20-Volt PDF

    HEF4093BP

    Abstract: hef4093 HEF4093BT HEF4093BP applications HEF4093B HEF4093BPN HEF4093BD MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER IN logic gates circuit diagram HEF4093BTD
    Text: HEF4093B gates J QUADRUPLE 2-INPUT NAND SCHMITT TRIGGER The HEF4093B consists o f four Schmitt-trigger circuits. Each circuit functions as a two-input NAND gate with Schmitt-trigger action on both inputs. The gate switches at different points for positive and


    OCR Scan     		HEF4093B 7Z73704 HEF4093BP 14-lead OT27-1) HEF4093BD HEF4093BT hef4093 HEF4093BP applications HEF4093BPN MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER IN logic gates circuit diagram HEF4093BTD PDF

    Untitled

    Abstract: No abstract text available
    Text: Macro-Embedded Type Celt Arrays • CE46 Series Features High integration: Technology: Gate delay time: Maximum 198,084 BCs on chip Si-gate CMOS, 2-layer metal Standard gate tpd=360 ps (2-input NAND, standard load, V dd=5 V) tpd=520 ps (2-input NAND, standard load, V dd=3.3 V)


    OCR Scan     		PDF