Contextual Info: SN54ALS2242, S N74ALS2242 Q U A D R U P L E BUS T R A N S C E IV E R S /M O S DRIVER M A Y 1 9 8 5 -R E V IS E D M A Y 1 9 8 6 Bidirectional Quadruple Bus Transceivers For Driving MOS Devices S N 5 4 A L S 2242 . . . J PACKAGE SN74A LS2242 . . . D OR N PACKAGE

74ALS653

Abstract: 74ALS654
Contextual Info: SN54ALS651 THRU SN54ALS654, SN54AS651, SN54AS652 S N74ALS651 THRU S N 74ALS65 4, S N 74 A S 6 5 1 , SN74AS652 O CTAL BUS TRANSCEIVERS AN D REGISTERS D 2 6 6 1 , DECEMBER 1 9 8 3 -R E V IS E D M A Y 1 9 8 6 • Bus Transceivers/Registers • Independent Registers and Enables for A

D2825

Abstract: SN74ALS845 SO7D 12N19 SN54ALS845
Contextual Info: SN54ALS845, SN54AS845. SN54ALS846, SN54AS846 S N74ALS845 , SN74AS845, N74ALS846. SN74AS846 8 B IT B U S I N T E R F A C E D T Y P E L A T C H E S W IT H 3 S T A T E O U T P U T S D 2 8 2 5 , D E C E M B E R 1 9 6 3 — R E V IS E D J A N U A R Y 1 9 8 6 S N 5 4 A L S 8 4 5 . S N 5 4 A S 8 4 5 . . . JT PACKAGE

SN74ALS638A

Abstract: SN74ALS639A SN74AS639 ASG39 d226 B628
Contextual Info: SN54ALS638A, SN54ALS639A, SN54AS638. SN54AS639 S N74ALS 638 A, S N74ALS 639A, SN74AS6 38 , SN74AS639 O C T A L BUS T R A N S C EIV ER S D 2 2 6 1 , DECEM BER 1 9 8 3 - R E V IS E D M A Y 1 9 8 6 S N 5 4 A L S ', S N 5 4 A S ' . . J P AC KA G E S N 7 4 A L S ’ , S N 7 4 A S ' . . . D W OR N PAC KA G E

sn54als164

Abstract: SN74ALS164
Contextual Info: SN54ALS164, N74ALS1G4 8 BIT PARALLEL OUT SERIAL SHIFT REGISTERS PRODUCT PREVIEW D 2 6 6 1 , A P R IL 1 9 8 2 - R E V I S E D M A Y 1 9 8 6 SN54ALS16 4 S N74ALS16 4 . . • A N D -G a te d E nable/D isab le Serial Inputs • Fully B uffered C lock and Serial Inputs

Contextual Info: SN54ALS259, N74ALS259 8 BIT AD D R E S S A B LE LA TC HES D2661, DECEMBER 1982-REVISED MAY 1986 S N 5 4 A L S 2 5 9 . J PACKAGE S N 7 4 A L S 2 5 9 . . . D OR N PACKAGE 8-Bit Parallel-Out Storage Register Performs Serial-to-Parallel Conversion with Storage

20 pin zif socket

Abstract: MS-012-AB 74ALS 74ALS377 N74ALS377D N74ALS377N TEXTOOL SOCKET DIP16 26 SIGNETICS TEXTOOL zif socket
Contextual Info: Signetics 74ALS377 Flip-Flop Octal D Flip-Flop With Enable Preliminary Specification ALS Products FEATURES • Ideal for addressable register applications • Enable for address and data syn­ chronization applications • Eight edge-triggered D-type flipflops

E530

Abstract: MS-012-AB 74ALS 74ALS273 N74ALS273D N74ALS273N 26 SIGNETICS
Contextual Info: Signetics 74ALS273 Flip-Flop Octal D Flip-Flop Preliminary Specification ALS Products FEATURES • Eight edge-triggered O-type flipflops • Buffered common clock • Buffered asynchronous Master Reset • See 'ALS377 for clock enable version TYPICAL fMAX

2BN5

Abstract: 74ALS03B
Contextual Info: S N 54A LS03B, SN 74 A LS0 3B QUADRUPLE 2 INPUT POSITIVE NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS M A R C H 1 9 8 4 —REVISED M A Y 1 9 8 6 • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mll

als641a

Abstract: S645
Contextual Info: N74ALS640B, N74ALS641A, N74ALS642A, N74ALS645A, SN74AS640, SN74AS641, SN74AS645 SN54ALS640B, SN54ALS645A, SN54AS640, SN54AS645 OCTAL BUS TRANSCEIVERS 02661, DECEMBER 1983 - REVISED APRIL 1987 Bidirectional Bus Transceivers In HlghDensity 20-Pin Packages

Contextual Info: 8-BIT N74ALS164 PARALLEL-OUT SERIAL SHIFT REGISTERS D2M1. APRIL 1982 - REVISED JANUARY 1989 AND-Gated Enable/Citable Serial Input* S N 7 4 A L 8 W 4 . . . D OR N PACKAGE (TO P V IE W ) Fully Buffered Clock and Serial Input* Direct Clear Package Option* Include Plaatlc "Smalt

TEXTOOL zif socket

Abstract: MS-012-AB 74ALS 74ALS74A ALS74A N74ALS74AD N74ALS74AN SOL-24
Contextual Info: Signetics 74ALS74A FLIP-FLOP 74ALS74A Dual D-Type Flip-Flops with Set and Reset Product Specification ALS Products DESCRIPTION T h e 'A LS 74A is a dual edge-triggered D type flip-flop featuring individual data, Set and R es e t inputs, with_true and com ple­

SN74ALS620A

Abstract: SN74ALS621A SN74ALS623A SN74AS623 b1039 als623a
Contextual Info: N74ALS620A, N74ALS621A, N74ALS623A, SN74AS623 OCTAL BUS TRANSCEIVERS D2661, DECEMBER 1982 - REVISED OCTOBER 1991 • Package Options Include Plastic "Small Outline" Packages and Standard Plastic 300-mil DIPs S N 7 4A LS '. S N 7 4 A S ' . . . Choice of True or Inverting Logic

74ALS193

Abstract: MR 1501 RT 1601 a LCD MS-012-AB 74ALS N74ALS193D N74ALS193N SOL-24
Contextual Info: Signetics 74ALS193 Counter Synchronous Presettable 4-Bit Binary Counter With Seperate Up and Down Clocks Preliminary Specification ALS Products TYPE TYPICAL f M*x TYPICAL SUPPLY CURRENT TOTAL FEATURES • Synchronous, reversible counting • Asynchronous parallel load capa­

5555 FAIRCHILD optocoupler

Abstract: MC74HC374N 74hc14n equivalent NC7S125M5 14069 HCF4541BEY APPLICATION HCF4013BE 4026 fairchild datasheet 14543 motorola Motorola DM74LS139N
Contextual Info: R E L I A B L E . L O G I C . I N N O V A T I O N . Logic Cross-Reference Logic Cross-Reference 2003 Texas Instruments Printed in the U.S.A. by Texoma Business Forms, Durant, Oklahoma Printed on recycled paper. SCYB017A NEW First Revision Logic Cross-Reference

SN74ALS880A

Contextual Info: SN54ALS880A, SN54AS880, N74ALS880A, SN74AS880 D U A L 4-BIT D T Y P E L A T C H E S W ITH 3 S T A T E O U T P U T S D 2 6 6 1 , DECEMBER 1 9 8 2 - REVISED M A Y 1 9 8 6 S N 54A LS880A, S N 54A S880 JT PACKAGE S N 74A LS880A. S N 74A S880 . . . DW OR NT PACKAGE

SN54ALS15A

Abstract: SN74ALS15A
Contextual Info: I f . 0 7 '-! SN54ALS15A, N74ALS15A TRIPLE 3 INPUT POSITIVE AND GATES WITH OPEN-COLLECTOR OUTPUTS M A R C H 1 9 8 4 — R E V IS E D M A Y 1 9 8 6 • S N 5 4 A L S 1 5 A . . . J PACKAGE S N 7 4 A L S 1 5 A . . . D OR N P AC KA G E P ackage O p tion s In clude Plastic " S m a ll

SN54ALS112A

Abstract: SN74 SN74ALS112A
Contextual Info: SN54ALS112A, N74ALS112A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D 2 6 6 1 , A P R IL 1 9 8 2 — R E V IS E D M A Y 1 9 8 6 • Fully Buffered to Offer Maxim um Isolation from External Disturbance • Package Options Include Plastic "Sm all

74ALS

Abstract: 74ALS377 N74ALS377D N74ALS377N
Contextual Info: 74ALS377 Flip-Flop Octal D Flip-Flop With Enable Preliminary Specification FEATURES • Ideal for addressable register applications • Enable for address and data syn­ chronization applications • Eight edge-triggered D-type flip­ flops • Buffered common clock

74ALS

Abstract: 74ALS253 N74ALS253D N74ALS253N
Contextual Info: 74ALS253 Multiplexer Dual 4-Input Multiplexer 3-State Preliminary Specification FEATURES • 3-state outputs for bus interface and m ultiplex expansion • Com m on select Inputs TYPICAL SUPPLY CURRENT (TOTAL) TYPICAL PROPAGATION DELAY TYPE • Separate Output Enable Inputs

Contextual Info: M M O T O R O L A TYPES SN54ALS02, N74ALS02 QUADRUPLE 2 INPUT POSITIVE NOR GATES d e scrip tio n These devices con ta in fo u r inde penden t 2 -in p u t NOR g a te s . They p e rfo rm th e b o o le a n (TOP VIEW) fu n c tio n s Y = A + B or Y = A-B in p o s itiv e logic.

SN74ALS123

Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
Contextual Info: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS

74als871

Abstract: 74AS870 74ALS870 74as871 2A3J
Contextual Info: SN54ALS870, SN54AS870, SN 5 4ALS 8 71, SN54AS871 S N 74 ALS 870, SN74AS870, S N 7 4 A L S 8 7 1 , SN 74AS 8 71 DUAL 16-BY-4 REGISTER FILES D 2 6 6 1 , DECEMBER 1 9 8 2 - REVISED M A Y 1 9 8 6 S N 5 4 A L S 8 7 0 , S N 5 4 A S 8 7 0 . . . J T PACKAGE S N 7 4 A L S 8 7 0 , S N 7 4 A S 8 7 0 . . . D W OR N T PACKAGE

B117H

Contextual Info: N74ALS620A, N74ALS621A, N74ALS623A, SN74AS623 OCTAL BUS TRANSCEIVERS D2661, DECEMBER 1982 - REVISED OCTOBER 1991 Package Options Include Plastic "Small Outline" Packages and Standard Plastic 300-mil DIPs S N 7 4A LS ’ . S N 7 4A S . . . D W OR N PACKAGE