API NETWORKS
Abstract: E9000 Marvell MIPS64 RM9200A
Text: RM9200A Released AM Integrated Multiprocessor DUAL E9000 CORES CACHE AND I/O COHERENCY PMC-Sierra’s RM9200A Integrated Processor is a high performance 64-bit MIPS-based dual-microprocessor with integrated memory and I/O interfaces. Each core provides: • 1 GHz operating frequency.
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RM9200A
E9000
RM9200A
64-bit
16-Kbyte,
256-Kbyte,
64-Entry
PMC-2040956
API NETWORKS
Marvell
MIPS64
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NII53001-7
Abstract: No abstract text available
Text: 12. Mailbox Core NII53001-7.1.0 Core Overview Multiprocessor environments can use the mailbox core with Avalon interface to send messages between processors. The mailbox core contains mutexes to ensure that only one processor modifies the mailbox contents at a time. The mailbox core must be used
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verilog code parity
Abstract: 1 wire verilog code BUS BAR specification palasm tri state PAR64
Text: PCI Bus Applications April 1995, ver. 1 Introduction In Altera Devices Application Note 41 The peripheral component interconnect PCI bus is designed for multiprocessor systems and high-performance peripherals, including audio and video systems, network adapters, graphics accelerator boards,
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SMD MARKING CODE A00b
Abstract: mil-std-1750a MARKING CODE A00B MIL-PRF-38510 as3 SMD Transistor MIL-STD-1750 ttl nim marking a00b SMD A009 pir chip
Text: Standard Products UT1750AR RadHard RISC Microprocessor Data Sheet May 2003 FEATURES q Operates in either RISC Reduced Instruction Set Computer mode or MIL-STD-1750A mode q Built-in multiprocessor bus arbitration and Direct Memory Access support (DMA) q Supports MIL-STD-1750A 32-bit floating-point
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UT1750AR
MIL-STD-1750A
32-bit
48-bit
MIL-PRF-38535
64K-word
SMD MARKING CODE A00b
MARKING CODE A00B
MIL-PRF-38510
as3 SMD Transistor
MIL-STD-1750
ttl nim
marking a00b
SMD A009
pir chip
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IVG10
Abstract: B08 REGULATOR
Text: Blackfin Embedded Symmetric Multiprocessor ADSP-BF561 a FEATURES PERIPHERALS Dual symmetric 600 MHz high performance Blackfin cores 328K bytes of on-chip memory see memory information on Page 4 Each Blackfin core includes: Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
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16-bit
40-bit
256-ball
297-ball
ADSP-BF561
IVG10
B08 REGULATOR
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CQFP
Abstract: smd diode JC applications guide 5962-9750601HXC AD14060BF-4 AD14060LBF-4 36c smd
Text: MultiChip Products Business Unit - Digital Products Selection Guide Page 1 of 1 MultiChip Products Business Unit - Digital Products Selection Guide Part Number Description Key Specifications Package Supply Power Theta-JC AD14060BF-4 Quad-SHARC Multiprocessor DSP
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AD14060BF-4
480MFLOPS;
480MBPS
16Mbit
308-CQFP
5962-9750601HXC
CQFP
smd diode JC
applications guide
5962-9750601HXC
AD14060BF-4
AD14060LBF-4
36c smd
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Untitled
Abstract: No abstract text available
Text: White Paper: Virtex-II Series R WP162 v1.1 April 10, 2003 Multiprocessor Systems By: Jeremy Kowalczyk With the availability of the Virtex-II Pro devices containing more than one Power PC processor and MicroBlaze™ and PicoBlaze™ soft processor cores, it
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WP162
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6120-37
Abstract: what is pson gt64260 GT-64260 C219 C320 gt64260a GT-64260A Part Numbering System transformer Tyco H1102 application note
Text: Errata MVPX2ERR/D Rev. D, 3/2002 MVP X2 Multiprocessor Evaluation System Errata 1 Introduction This document describes the known errata and limitations of the MVP reference platform. In all cases, if an errata has a workaround, it is applied to the system before shipped to customers.
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DECIMATION IN FREQUENCY DSP
Abstract: BUTTERFLY DSP fft algorithm SRAM 6116 two butterflies AN-42 IDT6116 IDT7052 IDT7054 IDT7210
Text: USING THE IDT7052/7054 FOURPORT SRAMs IN DSP AND MATRIX PROCESSING APPLICATIONS APPLICATION NOTE AN-42 By Tao Lin, Julie Lin, and Yupling Chung Introduction C Most digital signal processing DSP algorithms have inherent parallelism and may be pipelined. Usually, these algorithms are computation intensive. In real-time applications, multiprocessor or parallel distributed processor systems are commonly used to implement these
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IDT7052/7054
AN-42
IDT7052
IDT7054
AN-23.
AN-35.
DECIMATION IN FREQUENCY DSP
BUTTERFLY DSP
fft algorithm
SRAM 6116
two butterflies
AN-42
IDT6116
IDT7052
IDT7054
IDT7210
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74S161
Abstract: PLS Philips handbook GB2-100 transistor w04 AN07 74S138 74s161n 101XXX 03Dh
Text: INTEGRATED CIRCUITS AN07 Single chip multiprocessor arbiter 1993 Oct 01 Philips Semiconductors Philips Semiconductors Programmable Logic Devices Application Note Single chip multiprocessor arbiter AN07 INTRODUCTION ARBITER STRUCTURE In multiprocessor environments there is
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BUTTERFLY DSP
Abstract: AN-42 IDT6116 IDT7052 IDT7054 IDT7210 IDT7381 fft algorithm
Text: USING THE IDT7052/7054 FOURPORT SRAMs IN DSP AND MATRIX PROCESSING APPLICATIONS APPLICATION NOTE AN-42 By Tao Lin, Julie Lin, and Yupling Chung Introduction C Most digital signal processing DSP algorithms have inherent parallelism and may be pipelined. Usually, these algorithms are computation intensive. In real-time applications, multiprocessor or parallel distributed processor systems are commonly used to implement these
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IDT7052/7054
AN-42
IDT7052
IDT7054
AN-23.
AN-35.
BUTTERFLY DSP
AN-42
IDT6116
IDT7052
IDT7054
IDT7210
IDT7381
fft algorithm
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TSR 3-1250
Abstract: multi-processor
Text: APPLICATION NOTE H8/300L SLP Series Multiprocessor Communication Introduction Data transmission is performed via the serial communication interface using the multiprocessor communication function of the H8/38024. Transmit data format is specified as 8-bit length followed by a multiprocessor bit and a stop
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H8/300L
H8/38024.
H8/38024
REJ06B0250-0100Z/Rev
TSR 3-1250
multi-processor
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renesas label format
Abstract: No abstract text available
Text: APPLICATION NOTE H8S Family Multiprocessor Communication Introduction Uses the H8S/2339 multiprocessor function to transmit and receive data asynchronously, sharing a serial communication line with an H8S/2339 and an H8/2215 units. Target Device H8S/2339, H8S/2215
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H8S/2339
H8/2215
H8S/2339,
H8S/2215
REJ06B0461-0100/Rev
renesas label format
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Untitled
Abstract: No abstract text available
Text: DATA SHEET 3200 Series 10Gbps Ethernet-to-PCIe Intelligent Ethernet Adapters Overview The QLogic 3200 Series Adapters boast industry-leading Ethernet performance, achieving dual-port, line-rate 10-gigabit Ethernet GbE throughput. This extreme performance eliminates potential I/O bottlenecks in today’s powerful multiprocessor, multicore servers. In
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10Gbps
10-gigabit
10GbE
40Gbps
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Untitled
Abstract: No abstract text available
Text: CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V 16 K / 32 K / 64 K / 128 K x 9 Low-Voltage Deep Sync FIFOs Features buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. 3.3 V operation for low-power consumption and easy
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CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
CY7C4261V)
CY7C4271V)
CY7C4281V)
CY7C4291V)
35-micron
100-MHz
10-ns
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arbiter decoder -1996
Abstract: No abstract text available
Text: PCI Bus Applications April 1995, ver. 1 Introduction in Altera Devices Application Note 41 The peripheral component interconnect PCI bus is designed for multiprocessor systems and high-performance peripherals, including audio and video systems, network adapters, graphics accelerator boards,
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B1189
Abstract: mil-std-1750a MME transistor 401 4AX4 MIL-STD-1750 STD-1750A SI T37B t34l UT1750AR
Text: Standard Products UT1750AR RadHard RISC Microprocessor Data Sheet November 2000 FEATURES q Operates in either RISC Reduced Instruction Set Computer mode or MIL-STD-1750A mode q Built-in multiprocessor bus arbitration and Direct Memory Access support (DMA)
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UT1750AR
MIL-STD-1750A
32-bit
48-bit
MIL-PRF-38535
64K-word
144-Pin
MIL-PRF-38510.
B1189
MME transistor 401
4AX4
MIL-STD-1750
STD-1750A
SI T37B
t34l
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RM9224
Abstract: DDR PHY ASIC MIPS64 "network interface cards" 896-pin pmc
Text: RM9224 Released RM9224 Integrated Multiprocessor FEATURES CACHE AND I/O COHERENCY The RM9224 Integrated Multiprocessor builds on the success of PMC-Sierra's next generation MIPS-based E9K processors by providing features specifically suited for network processing applications. It provides:
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RM9224
RM9224
PMC-2021863
DDR PHY ASIC
MIPS64
"network interface cards"
896-pin pmc
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82489DX AP-388
Abstract: 82489dx intel 82357 intel 82489dx
Text: 82489DX ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER 82489DX FEATURES OVERVIEW • Inter-Processor Interrupts ■ Advanced Interrupt Controller for 32-Bit Operating Systems ■ Various Addressing Schemes— Broadcast, Fixed, Lowest Priority, etc. ■ Solution for Multiprocessor Interrupt
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82489DX
82489DX
32-Bit
132-Lead
82489DX.
82489DX AP-388
intel 82357
intel 82489dx
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Speed PI Controller
Abstract: AP 138B 114H 80960MC M82965
Text: AP-Bus Interface Using the BXU CHAPTER 8 AP-BUS INTERFACE USING THE BXU The M82965 Bus Extension Unit BXU is the key component in building multiprocessor designs with the 80960MC processor family. The BXUs connect to each other in an expandable matrix that
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M82965
80960MC
Speed PI Controller
AP 138B
114H
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eb31
Abstract: P2A13 D2688 16k x 1 ram
Text: ADVANCE INFORMATION IDT 7MB6049 DUAL 16K x 60 DATA/ INSTRUCTION CACHE MODULE FOR IDT79R3000 CPU (MULTIPROCESSOR) FEATURES: DESCRIPTION: • High-speed CMOS static RAM module constructed to support the IDT79R3000 CPU in a multi-processor system as a complete data and instruction cache (dual 16K x 60)
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IDT79R3000
12MHz,
20MHz
25MHz
IDT79R3000
120-pin
7MB6049
IDT7MB60be
DSC-7044/-
eb31
P2A13
D2688
16k x 1 ram
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80960MC
Abstract: multi-processor
Text: 80960MC Multiprocessor System Architecture Q CHAPTER 6 80960MC MULTIPROCESSOR SYSTEM ARCHITECTURE This chapter illustrates the flexibility of the 80960MC system architecture using the advanced 32bit 80960MC processor and the 82965 Bus Extension Unit BXU in a multiprocessor design.
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80960MC
32-bit
multi-processor
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R3000A
Abstract: mips r3000 pin diagram R3010 mips processor MIPS R3000A
Text: Integrated Device Technology* Inc. R3000 CPU MODULES FOR HIGH PERFORMANCE AND MULTIPROCESSOR SYSTEMS FEATURES: • Cache Size: 64K Instruction, 64K Data • Processor Speeds up to 33 MHz • Includes R3010 Floating Point Accelerator • 1-word Read Buffer; 4-word Write Buffer
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R3000
IDT7RS107
R3010
IDT7RS107
7RS107F66A25A
S107F66A
R3000A
mips r3000 pin diagram
R3010 mips processor
MIPS R3000A
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Untitled
Abstract: No abstract text available
Text: Microprocessor Peripherals UPI-41A/41AH/42/42AH User’s Manual CONTENTS page CHAPTER 1. INTRODUCTION 4-3 Interface Registers for Multiprocessor Configurations . 4-5 Powerful 8-Bit Processor . 4-5
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UPI-41A/41AH/42/42AH
UPI-41AH/42AH
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