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    MULTI-RATE FIR FILTERS Search Results

    MULTI-RATE FIR FILTERS Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    NFMJMPC226R0G3D Murata Manufacturing Co Ltd Data Line Filter, Visit Murata Manufacturing Co Ltd
    NFM15PC755R0G3D Murata Manufacturing Co Ltd Feed Through Capacitor, Visit Murata Manufacturing Co Ltd
    NFM15PC435R0G3D Murata Manufacturing Co Ltd Feed Through Capacitor, Visit Murata Manufacturing Co Ltd
    NFM15PC915R0G3D Murata Manufacturing Co Ltd Feed Through Capacitor, Visit Murata Manufacturing Co Ltd
    SF-XP85B102DX-000 Amphenol Cables on Demand Amphenol SF-XP85B102DX-000 SFP28 25GBASE-SR Short-Range 850nm Multi-Mode Optical Transceiver Module (Duplex LC Connector) by Amphenol XGIGA [XP85B102DX] Datasheet

    MULTI-RATE FIR FILTERS Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    TMS 3834

    Abstract: 40298 DS6-12F digital filter sinc filter CS4373 CS5376 CS5376A CS5376A-IQ geophone detector
    Text: CS5376A Low Power Multi-Channel Decimation Filter Features Description 1 to 4 Channel Digital Decimation Filter Multiple On-Chip FIR and IIR Coefficient Sets Programmable Coefficients for Custom Filters Synchronous Operation Selectable Output Word Rate 4000, 2000, 1000, 500, 333, 250 SPS


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    PDF CS5376A CS5376A CS3301/02 CS5371/72 CS4373 TMS 3834 40298 DS6-12F digital filter sinc filter CS4373 CS5376 CS5376A-IQ geophone detector

    digital FIR Filter VHDL code

    Abstract: verilog code for interpolation filter code iir filter in vhdl verilog code for decimation filter digital FIR Filter verilog code application circuit for FIR filter matlaB design FIR filter matlaB design FIR Filter verilog code 00D8 EP3C16F484C6
    Text: FIR Compiler II MegaCore Function User Guide FIR Compiler II MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01072-2.0 Document last updated for Altera Complete Design Suite version: Document publication date: 10.0 July 2010


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    PDF UG-01072-2 digital FIR Filter VHDL code verilog code for interpolation filter code iir filter in vhdl verilog code for decimation filter digital FIR Filter verilog code application circuit for FIR filter matlaB design FIR filter matlaB design FIR Filter verilog code 00D8 EP3C16F484C6

    QF1Da512

    Abstract: HBM 00-07H DSDI audio crossover filter Transistor FIR 3D 41 AEC-Q100-002D qf1d512 QF1D512-DK dr2m circuit for 7.1 home theatre system
    Text: PRELIMINARY DATA SHEET QF1Da512 Simple and versatile FIR engine SavFIReTM APPLICATIONS • Audio Equalization, Crossovers, and 3D widening  Televisions Clk Gen CTRL Registers clk_sys  Docking Stations  Stereo Headsets (both wired and wireless)  Home Theatre Speakers


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    PDF QF1Da512 QF1Da512 HBM 00-07H DSDI audio crossover filter Transistor FIR 3D 41 AEC-Q100-002D qf1d512 QF1D512-DK dr2m circuit for 7.1 home theatre system

    verilog code for interpolation filter

    Abstract: verilog code for decimation filter digital FIR Filter verilog code digital FIR Filter VHDL code verilog code for fir filter digital Serial FIR Filter VHDL for decimation filter c code for interpolation and decimation filter FIR Filter verilog code verilog code for serial multiplier
    Text: Serial FIR Filter User’s Guide April 2003 ipug13_01 Lattice Semiconductor Serial FIR Filter User’s Guide Introduction The Serial FIR Filter core is one of two FIR cores supported by Lattice. This core is an area-efficient implementation that uses serial arithmetic elements to achieve compact size.


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    PDF ipug13 1-800-LATTICE verilog code for interpolation filter verilog code for decimation filter digital FIR Filter verilog code digital FIR Filter VHDL code verilog code for fir filter digital Serial FIR Filter VHDL for decimation filter c code for interpolation and decimation filter FIR Filter verilog code verilog code for serial multiplier

    Untitled

    Abstract: No abstract text available
    Text: ispLever CORE TM Serial FIR Filter User’s Guide October 2005 ipug13_02.0 Lattice Semiconductor Serial FIR Filter User’s Guide Introduction The Serial FIR Filter core is one of two FIR cores supported by Lattice. This core is an area-efficient implementation that uses serial arithmetic elements to achieve compact size.


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    PDF ipug13

    AK4351

    Abstract: 18-BIT high order lpf
    Text: ASAHI KASEI [AK4351] AK4351 18Bit Advanced Multi Bit DS 2ch DAC GENERAL DESCRIPTION The AK4351 is a high cost performance 18bit stereo DAC for low-end digital audio systems. The modulator in the AK4351 uses the new developed Advanced Multi Bit architecture with wide dynamic


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    PDF AK4351] AK4351 18Bit AK4351 16pin 50kHz 18-BIT high order lpf

    types of binary multipliers

    Abstract: Parallel FIR Filter APPLICATION circuit diagram fir filters implementing FIR and IIR digital filters types of multipliers DTH block diagram of internal parts iir filter diagrams
    Text: Parallel FIR Filter User’s Guide January 2003 ipug06_01 Lattice Semiconductor Parallel FIR Filter User’s Guide Introduction This document serves as a guide containing technical information about the Lattice Parallel FIR Filter core. Overview The Parallel FIR Filter core is one of two FIR cores supported by Lattice. This core is designed to perform filtering


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    PDF ipug06 1-800-LATTICE types of binary multipliers Parallel FIR Filter APPLICATION circuit diagram fir filters implementing FIR and IIR digital filters types of multipliers DTH block diagram of internal parts iir filter diagrams

    XAPP284

    Abstract: matrix converter FIR 3D matrix mux 3x3 matrix LF2272 XC4000E vhdl 3*3 matrix pipelined matrix multiplication fpga MULT18X18S
    Text: Application Note: Virtex-II Series R Matrix Math, Graphics, and Video Author: Latha Pillai XAPP284 v1.1 October 15, 2001 Summary Many pipelined functions in the computer graphics and video fields are expressed in matrix mathematics. This Matrix Multiplier application note describes a unique way to implement a


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    PDF XAPP284 XAPP284 matrix converter FIR 3D matrix mux 3x3 matrix LF2272 XC4000E vhdl 3*3 matrix pipelined matrix multiplication fpga MULT18X18S

    SCR FIR 3 D

    Abstract: AD7725 non-recursive filter digital signal processor
    Text: = 16-Bit Sigma-Delta ADC with PulseDSP* Post Processor Preliminary Technical Data FEATURES Programmable Signal Conditioning LowPass HighPass BandStop BandPass Programmable Decimation, Interpolation and Output Word Rate Flexible Programming Modes Boot ROM External EEPROM


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    PDF 16-Bit 44-Pin AD7725 AD7725 AD7725, SCR FIR 3 D non-recursive filter digital signal processor

    PDSP16256

    Abstract: PDSP16350 PDSP16510A
    Text: PDSP16256/A Programmable FIR Filter DS3709 Features ● ● ● ● ● ● ● Sixteen MACs in a Single Device Basic Mode is 16-Tap Filter at up to 25MHz Sample Rates Programmable to give up to 128 Taps with Sampling Rates Proportionally Reducing to 3•125MHz


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    PDF PDSP16256/A DS3709 16-Tap 25MHz 125MHz 16-bit 32-bit PDSP16256A/C0/AC 25MHz, PDSP16256 PDSP16350 PDSP16510A

    SCR FIR 3 D

    Abstract: capacitors chi da AD7725 7004 ad
    Text: a 16-Bit Sigma-Delta ADC with Programmable Post Processor Preliminary Technical Data The part provides an accurate on-chip 2.5V reference for the modulator. A reference input/output function is provided to allow either the internal reference or an external


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    PDF 16-Bit 44-pin -40oC SMODE1/DB15 SMODE0/DB14 AD7725, SCR FIR 3 D capacitors chi da AD7725 7004 ad

    INTERPOLATOR

    Abstract: 256fS
    Text: ASAHI KASEI [AK4380] AK4380 100dB 24Bit 96kHz 2ch DAC GENERAL DESCRIPTION The AK4380 offers the perfect mix for cost and performance based audio systems. Using AKM's multi bit architecture for its modulator the AK4380 delivers a wide dynamic range while preserving linearity for


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    PDF AK4380] AK4380 100dB 24Bit 96kHz AK4380 INTERPOLATOR 256fS

    simulink 16QAM

    Abstract: wireless power transfer matlab simulink wcdma simulink cic filter matlab design MISO Matlab code gain sensitive numerically controlled oscillator in matlab TAPPED DELAY LINE FILTER MIMO MIMO Matlab code hdl inverse sinc filter cic FIR filter matlaB simulink design
    Text: Tool Flow for Design of Digital IF for Wireless Systems Application Note 442 May 2007, version 1.0 Introduction This application note describes the tool flow that accelerates the hardware design of digital intermediate frequency IF systems comprising of


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    multiplier accumulator unit with VHDL

    Abstract: No abstract text available
    Text: Philips Semiconductors’ R.E.A.L. DSP Core for Low-Cost Low-Power Telecommunication and Consumer Applications Why consumer oriented DSP is different Without the advent of digital signal processing many of the latest Many consumer applications also call for a highly integrated implementa-


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    PDF SCB60 multiplier accumulator unit with VHDL

    fir compiler v5

    Abstract: ds534 DSP48 SRL16 XIP162 matched filter matlab codes fir compiler xilinx digital FIR Filter using distributed arithmetic MATLAB code for halfband filter fir compiler v4
    Text: FIR Compiler v3.2 DS534 October 10, 2007 Product Specification Features General Description • Highly parameterizable drop-in module for Virtex , Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, The Xilinx LogiCORE™ IP FIR Compiler core provides a common interface for users to generate highly parameterizable, area-efficient high-performance FIR filters


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    PDF DS534 fir compiler v5 DSP48 SRL16 XIP162 matched filter matlab codes fir compiler xilinx digital FIR Filter using distributed arithmetic MATLAB code for halfband filter fir compiler v4

    Untitled

    Abstract: No abstract text available
    Text: 2D FIR Filter IP Core User’s Guide January 2011 IPUG89_01.0 Table of Contents Chapter 1. Introduction . 4 Quick Facts . 4


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    PDF IPUG89 MULT18X18 LFXP2-40E-6F484C D-2010 03L-SP1

    mc1450

    Abstract: CS5326 DSP56000 MC14 MC145073 TMS320
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL Order this document by MC1450731D DATA - - MC145073 Product Preview DuaI 16-Bit Stereo Audio Sigma-DeIta ADC CMOS The MC1 45073 is a dual<hannel, 16–bit ND converter intended for use in digital audio systems such as multimedia, DCC, DAT, and professional audio


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    PDF MC1450731D MC145073 16-Bit MC145073~ mc1450 CS5326 DSP56000 MC14 MC145073 TMS320

    fm transmitter project report

    Abstract: TMS320C40 abstract for speaker to microphone converter radar sensor specification TMS320 sample project of adaptive filter implementation audio SELECTOR DPCC40 subband adaptive noise single stage fm transmitter project report
    Text: Disclaimer: This document was part of the DSP Solution Challenge 1995 European Team Papers. It may have been written by someone whose native language is not English. TI assumes no liability for the quality of writing and/or the accuracy of the information contained herein.


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    PDF TMS320C40 SPRA305 fm transmitter project report abstract for speaker to microphone converter radar sensor specification TMS320 sample project of adaptive filter implementation audio SELECTOR DPCC40 subband adaptive noise single stage fm transmitter project report

    FIR FILTER implementation xilinx

    Abstract: implementation of 16-tap fir filter using fpga
    Text: Distributed Arithmetic FIR Filter V3.0.0 July 5 2000 Product Specification Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 FAX: +1 408-559-7114 URL: www.xilinx.com/ipcenter Support: www.support.xilinx.com 1 Features • • • •


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    PDF 2-to-1024 1-to-32 FIR FILTER implementation xilinx implementation of 16-tap fir filter using fpga

    GSM circuit diagram project

    Abstract: GSM code by matlab 16Q16 VOCODERS sbas079 SPRA793 vocoder implementation MATLAB SPRA802 GSM project circuit VOCODER
    Text: Application Report SPRA875 – December 2002 Vocoders Integrated to RF3 TI Catalog Applications Team Sunil J B, Binesh B ABSTRACT This application report explains how TMS320C64x optimized vocoders are integrated to Reference Framework Level 3 RF3 on TEB6416. Reference Framework for eXpressDSP


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    PDF SPRA875 TMS320C64x TEB6416. TMS320 GSM circuit diagram project GSM code by matlab 16Q16 VOCODERS sbas079 SPRA793 vocoder implementation MATLAB SPRA802 GSM project circuit VOCODER

    ssm2142

    Abstract: professional microphone preamp dor msop DF1706 PCM3000 SSM2141 OPA343 Pacific Microsonics PCM1732 INA103
    Text: Audio Products LINEAR PRODUCTS Microphone Preamp Line Drivers/ Receivers INA103 Microphone Preamp Low Noise, Balanced Input DRV134, DRV135 Differential Line Driver Pin-for-Pin with SSM2142 Op Amps OPA343 Family Low Cost, CMOS, Rail-to-Rail Op Amps OPA353 Family


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    PDF INA103 DRV134, DRV135 SSM2142) OPA343 OPA353 INA134, INA2134 SSM2141) OPA134 ssm2142 professional microphone preamp dor msop DF1706 PCM3000 SSM2141 Pacific Microsonics PCM1732 INA103

    NJU26124

    Abstract: NJU26124 E 3-band equalizer JESD65 SSOP24 3 pins trimmer capacitor pin configuration
    Text: NJU26124 • General Description Digital Signal Processor for TV ■Package The NJU26124 is a high performance 24-bit digital signal processor. The NJU26124 provides 512TAP FIR Filter, PEQ and Time Alignment Delay. These kinds of sound functions are suitable for TV, mini-component, CD


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    PDF NJU26124 NJU26124 24-bit 512TAP NJU26124VC2 24bit NJU26124 E 3-band equalizer JESD65 SSOP24 3 pins trimmer capacitor pin configuration

    remez

    Abstract: cookbook approach adsp-1010 AN-344 frequency sampling method of digital fir filter implementing FIR and IIR digital filters remez exchange radar fir filter
    Text: ANALOG ► DEVICES AN-344 APPLICATION NOTE ONE TECHNOLOGY WAY • P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 617/329-4700 Digital Hr Filters Without Tears by Bill Windsor and Paul Toldaiagi Digital filters once required specialized design techniques, highperformance costly hardware, and complicated software to imple­


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    PDF AN-344 remez cookbook approach adsp-1010 frequency sampling method of digital fir filter implementing FIR and IIR digital filters remez exchange radar fir filter

    Untitled

    Abstract: No abstract text available
    Text: 2bE D LOGIC DEVICES INC • SSbSTQS 0G0127S 3 ■ T -9 B -Û 7 12-bit Cascadable Multiplier-Accumulator MM • LMS12 DESCRIPTION The LMS12 is a high speed 12 x 12-bit of the dock in the 12-bit A and B input combinatorial multiplier integrated register, respectively. These registers


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    PDF 0G0127S 12-bit LMS12 LMS12 26-bit 84-pin