MS00 MARKING Search Results

MS00 MARKING Result Highlights (5)

Part	ECAD Model	Manufacturer	Description	Download	Buy
5962-8950303GC		Rochester Electronics LLC	ICM7555M - Dual Marked (ICM7555MTV/883)
54HC221AJ/883C		Rochester Electronics LLC	54HC221AJ/883C - Dual marked (5962-8780502EA)
MG8097/B		Rochester Electronics LLC	8097 - Math Coprocessor - Dual marked (8506301ZA)
5490/BCA		Rochester Electronics LLC	5490 - Decade Counter - Dual marked (M38510/01307BCA)
5405/BCA		Rochester Electronics LLC	5405 - Gate - Dual marked (M38510/00108BCA)

MS00 MARKING Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A)	PDF
A115-A Abstract: C101 SN74AUC00 Text: SN74AUC00 QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATE SCES510 − NOVEMBER 2003 D Optimized for 1.8-V Operation and Is 3.6-V D 1B 1Y 2A 2B 2Y 1A VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 10 3B 9 3A 6 7 8 3Y D D D D D I/O Tolerant to Support Mixed-Mode Signal Operation	Original	SN74AUC00 SCES510 000-V A114-A) A115-A) A115-A C101 SN74AUC00	PDF
Untitled Abstract: No abstract text available Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A)	PDF
ms00 marking Abstract: No abstract text available Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A) ms00 marking	PDF
A115-A Abstract: C101 SN74AUC00 Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A) A115-A C101 SN74AUC00	PDF
A115-A Abstract: C101 SN74AUC00 Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A) A115-A C101 SN74AUC00	PDF
A115-A Abstract: C101 SN74AUC00 Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A) A115-A C101 SN74AUC00	PDF
Untitled Abstract: No abstract text available Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A)	PDF
Untitled Abstract: No abstract text available Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A)	PDF
A115-A Abstract: C101 SN74AUC00 Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A) A115-A C101 SN74AUC00	PDF
Untitled Abstract: No abstract text available Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A)	PDF
Untitled Abstract: No abstract text available Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A)	PDF
A115-A Abstract: C101 SN74AUC00 Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A) A115-A C101 SN74AUC00	PDF
Untitled Abstract: No abstract text available Text: SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 4B 3 12 4A 4 11 4Y 5 10 3B 9 3A 6 7 8 3Y • • • • • 1B 1Y 2A 2B 2Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O	Original	SN74AUC00 SCES510A 000-V A114-A) A115-A)	PDF