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    MQFPF256 Search Results

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    ERC32

    Abstract: TSC695 TSC695FL erc32 trap WE 251 d1899
    Text: Features • Integer Unit Based on SPARC V7 High-performance RISC Architecture • Optimized Integrated 32/64-bit Floating-point Unit • On-chip Peripherals • • • • • • • • • • • – EDAC and Parity Generator and Checker – Memory Interface


    Original     		PDF 32/64-bit 40-bit ERC32 TSC695 TSC695FL erc32 trap WE 251 d1899

    ERC32

    Abstract: erc32 trap TSC695 TSC695FL T2815 WE 251
    Text: Features • Integer Unit Based on SPARC V7 High-performance RISC Architecture • Optimized Integrated 32/64-bit Floating-point Unit • On-chip Peripherals • • • • • • • • • • • – EDAC and Parity Generator and Checker – Memory Interface


    Original     		PDF 32/64-bit 40-bit 4204C ERC32 erc32 trap TSC695 TSC695FL T2815 WE 251

    ATDH40M

    Abstract: FIGARO LM7805 M 5962-0325002QYC IN4001 diode INFORMATION AT17 AT17LV010 AT40KEL ATDH2225 ATMEl 837
    Text: AT40KEL-DK Design Kit . User Guide Table of Contents Section 1 Introduction . 1-1


    Original     		PDF AT40KEL-DK 4334C ATDH40M FIGARO LM7805 M 5962-0325002QYC IN4001 diode INFORMATION AT17 AT17LV010 AT40KEL ATDH2225 ATMEl 837

    ATF280

    Abstract: 4066c MQFP352 ATF280E 0.18 um CMOS Process MQFPF256 ATF280E-DK 4066C-AERO-07 0.18-um SRAM 5962-0325001VXC
    Text: AEROSPACE FPGA s on way 31 311 2600 ad on 00 69 Timbaud en- 0-00 71-11 wa Bldg. 4-0033 51 581 ests erature oration. mbinations You Are are registered elSim® and red trademarks orporation. uct names may ers. 07/09/2M ATF280 Reprogrammable Rad-hard FPGAs


    Original     		PDF 07/09/2M ATF280 ATF280 4066c MQFP352 ATF280E 0.18 um CMOS Process MQFPF256 ATF280E-DK 4066C-AERO-07 0.18-um SRAM 5962-0325001VXC

    dual-port RAM

    Abstract: AT17 AT17LV010-10DP AT40K MQFPF256 IO358
    Text: Features • Functionally and Pin Compatible with the Atmel Commercial and Military AT40K Series • Ultra High Performance • • • • • • • • • • • • • • – System Speeds 60 MHz – Array Multipliers > 32 MHz – 18 ns Flexible SRAM


    Original     		PDF AT40K AT40KEL040 4155F dual-port RAM AT17 AT17LV010-10DP MQFPF256 IO358

    DIGITAL IC TESTER report for project

    Abstract: atmel 504 IO33 ATC18RHA 4261C virage IO33
    Text: Features • Comprehensive Library of Standard Logic and I/O Cells • ATC18RHA Core and IO18 pads Designed to Operate with VDD = 1.8V +/- 0.15V as Main • • • • • • • • • • • • • • Condition IO33 Pad Libraries Provide Interfaces to 3.3+/-0.3V Environments


    Original     		PDF ATC18RHA 655Mbps) 4261C DIGITAL IC TESTER report for project atmel 504 IO33 ATC18RHA virage IO33

    7 bit hamming code

    Abstract: SPARC T4-2 TSC695FL-15MA TSC695FL-15MA-E FDN 305
    Text: Features • Integer Unit Based on SPARC V7 High-performance RISC Architecture • Optimized Integrated 32/64-bit Floating-point Unit • On-chip Peripherals • • • • • • • • • • • – EDAC and Parity Generator and Checker – Memory Interface


    Original     		PDF 32/64-bit 40-bit 4204B 7 bit hamming code SPARC T4-2 TSC695FL-15MA TSC695FL-15MA-E FDN 305

    IO358

    Abstract: AT17 AT17LV010-10DP AT40K MQFPF256 MQFP-256
    Text: Features • Functionally and Pin Compatible with the Atmel Commercial and Military AT40K Series • Ultra High Performance • • • • • • • • • • • • • • • – System Speeds 60 MHz – Array Multipliers > 32 MHz – 18 ns Flexible SRAM


    Original     		PDF AT40K AT40KEL040 4155G IO358 AT17 AT17LV010-10DP MQFPF256 MQFP-256

    MQFPL160

    Abstract: UD02 UD09 LCC100 QuickLogic Military FPGA Introduction UD10 atmel 336 20RA10 XC7000 PGA68
    Text: Digital Integration Design done by Customer and TEMIC MATRA MHS Digital Integration Introduction When integrating the digital part of modern electronic system, various technical and financial criteria are considered. Over 10 years of ASIC experience have shown


    Original     		PDF

    ADSP-21xxx

    Abstract: mrf 212 PGA223 ADSP-21000 ADSP21020 ADSP-21020 TSC21020F DMD30
    Text: Features • • • • • • • • • • • • • • • • • • • • • • • • • • Superscalar IEEE Floating-Point-Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 50 ns, 20 MIPS Instruction Rate, Single Cycle Execution


    Original     		PDF 1024-Point 32-bit 40-bit 80-bit 4153I ADSP-21xxx mrf 212 PGA223 ADSP-21000 ADSP21020 ADSP-21020 TSC21020F DMD30

    RY 227

    Abstract: ROUND ROBIN ARBITRATION AND FIXED PRIORITY "RY 227" at697f AT697F-KG-E 0722402VYC 5962-0722402vyc AT697 AT697F-2H-E ATC18RHA
    Text: Features • SPARC V8 High Performance Low-power 32-bit Architecture – 8 Register Windows • Advanced Architecture: • • • • • • • • • • • • • – On-chip Amba Bus – 5 Stage Pipeline – 16 kbyte Multi-sets Data Cache – 32 kbyte Multi-sets Instruction Cache


    Original     		PDF 32-bit Two32-bit 32-bitTimer 33MHz 32/64-bit 7703D RY 227 ROUND ROBIN ARBITRATION AND FIXED PRIORITY "RY 227" at697f AT697F-KG-E 0722402VYC 5962-0722402vyc AT697 AT697F-2H-E ATC18RHA

    MCGA-349

    Abstract: MQFPF196 988000
    Text: Pages 1 to 29 INTEGRATED CIRCUITS, SILICON MONOLITHIC, CMOS, GATE ARRAY/EMBEDDED ARRAY BASED ON TYPE MH1RT ESCC Detail Specification No. 9202/076 Issue 2 July 2007 Document Custodian: European Space Agency - see https://escies.org ESCC Detail Specification No. 9202/076


    Original     		PDF

    DIGITAL IC TESTER report for project

    Abstract: ATMEL 644 IO33 4261F ATC18RHA Genesys Logic MQFP-F196 5962-06B02 atmel 216 4261b
    Text: Features • • • • • • • • • • • • • • • • Comprehensive Library of Standard Logic and I/O Cells ATC18RHA Core pads Designed to Operate with VDD = 1.8V +/- 0.15V as Main Condition IO33 Pad Libraries Provide Interfaces to 3.3+/-0.3V and 2.5 +/- 0.25V Environments


    Original     		PDF ATC18RHA 655Mbps) 4261F DIGITAL IC TESTER report for project ATMEL 644 IO33 Genesys Logic MQFP-F196 5962-06B02 atmel 216 4261b

    IO358

    Abstract: IO149 AT17 AT17LV010-10DP AT40K MQFPF256 IO303 IO220 IO369
    Text: Features • Functionally and Pin Compatible with the Atmel Commercial and Military AT40K Series • Ultra High Performance • • • • • • • • • • • • • • – System Speeds 60 MHz – Array Multipliers > 32 MHz – 18 ns Flexible SRAM


    Original     		PDF AT40K AT40KEL040 4155C IO358 IO149 AT17 AT17LV010-10DP MQFPF256 IO303 IO220 IO369

    DIGITAL IC TESTER report for project

    Abstract: MCGA349 PL33RXZ atmel 504 ATMEL 644 ATC18RHA 5962-06B02 MQFP-T352 IO33 mcga
    Text: Features • • • • • • • • • • • • • • • • Comprehensive Library of Standard Logic and I/O Cells ATC18RHA Core pads Designed to Operate with VDD = 1.8V +/- 0.15V as Main Condition IO33 Pad Libraries Provide Interfaces to 3.3+/-0.3V and 2.5 +/- 0.25V Environments


    Original     		PDF ATC18RHA 655Mbps) 4261E DIGITAL IC TESTER report for project MCGA349 PL33RXZ atmel 504 ATMEL 644 5962-06B02 MQFP-T352 IO33 mcga

    amd 29050

    Abstract: VHDL CODE FOR PID CONTROLLERS 20630 Xilinx XC2000 LCC100 UD09 LCC84 UD10 8251 uart vhdl MCT8
    Text: Digital Integration Introduction When integrating the digital part of modern electronic systems, various technical and financial criteria must be considered. Over 10 years of ASIC experience have shown that no one methodology can meet all requirements at the same time.


    Original     		PDF 10-May-96 amd 29050 VHDL CODE FOR PID CONTROLLERS 20630 Xilinx XC2000 LCC100 UD09 LCC84 UD10 8251 uart vhdl MCT8

    Untitled

    Abstract: No abstract text available
    Text: Features • Integer Unit Based on SPARC V7 High-performance RISC Architecture • Optimized Integrated 32/64-bit Floating-point Unit • On-chip Peripherals • • • • • • • • • • • – EDAC and Parity Generator and Checker – Memory Interface


    Original     		PDF 32/64-bit 40-bit 4118Iâ

    7 bit hamming code

    Abstract: TSC695FL ERC32 TSC695 TSC695FL PINS d2590
    Text: Features • Integer Unit Based on SPARC V7 High-performance RISC Architecture • Optimized Integrated 32/64-bit Floating-point Unit • On-chip Peripherals • • • • • • • • • • • – EDAC and Parity Generator and Checker – Memory Interface


    Original     		PDF 32/64-bit 40-bit 4204C 7 bit hamming code TSC695FL ERC32 TSC695 TSC695FL PINS d2590

    MQFPF256

    Abstract: 4066A SMD to6 5962-0325001QXC AT17LV010-10DP AT40K AT40KAL AT40KEL040KW1-E MQFPF-256 fpga radiation
    Text: A E R O S PA C E AT40KEL040 Reprogrammable Rad-hard FPGAs with Built-in SEU Protection FPGA AT 4 0 K E L 0 4 0 R E - P R O G R A M M A B L E SEU H A R D E N E D FPGA S For low gate count designs, the space market trends towards reprogrammable FPGAs. Capitalizing


    Original     		PDF AT40KEL040 AT40KEL040, 066A-AERO-04/04/10M MQFPF256 4066A SMD to6 5962-0325001QXC AT17LV010-10DP AT40K AT40KAL AT40KEL040KW1-E MQFPF-256 fpga radiation

    ADSP-21xxx

    Abstract: ADSP-21000 ADSP21020 ADSP-21020 TSC21020F
    Text: Features • • • • • • • • • • • • • • • • • • • • • • • • • Superscalar IEEE Floating-Point-Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 50 ns, 20 MIPS Instruction Rate, Single Cycle Execution


    Original     		PDF 1024-Point 32-bit 40-bit 80-bit 4153F ADSP-21xxx ADSP-21000 ADSP21020 ADSP-21020 TSC21020F

    MQFPF256

    Abstract: LCC68
    Text: Tem ic S e m i c o n d u c t o r s PLCC28 S 028 On-Board Computers Part Number Function Key Features Package Source TSC691E 32-bit SPARC computer: integer unit Radiant tolerant, 10 Mips @ 14 MHz, JTAG interface MQFPF256 NT TSC692E 32-bit SPARC computer: floating-point unit


    OCR Scan     		PDF PLCC28 TSC691E 32-bit MQFPF256 TSC692E MQFPF160 TSC693E 656XX LCC68

    en1 3009

    Abstract: 56KQ MQFP-F256 EM 222 raft pd TSC695F uart example used in k60 l17h 2360D
    Text: INTEGRATED CIRCUITS, SILICON MONOLITHIC, 32-BIT SPARC EMBEDDED PROCESSOR, BASED ON TYPE TSC695F ESCC Detail Specification No. 9512/003 ISSUE 1 February 2004 esa = 11 ss = -i- 1 1 1 iis = a ii: a Document Custodian: European Space Agency - see https://escies.org


    OCR Scan     		PDF 32-BIT TSC695F en1 3009 56KQ MQFP-F256 EM 222 raft pd TSC695F uart example used in k60 l17h 2360D

    MQFPL160

    Abstract: No abstract text available
    Text: T em ic MG2RT Semiconductors Radiation Tolerant 0.5-jiim CMOS Sea-of-Gates 100k Rad Low Dose Rate Introduction The MG2RT series is a 0.5 micron, array based, CMOS product family. Several arrays up to 700k cells cover all system integration needs. The MG2RT is manufactured


    OCR Scan     		PDF OAI22 MQFPL160

    PMA18

    Abstract: TSC21020F IRQ30 21020F
    Text: INTEGRATED CIRCUITS, SILICON MONOLITHIC, CMOS 32/40-BIT IEEE FLOATING POINT DIGITAL SIGNAL PROCESSOR, BASED ON TYPE TSC 21020 F ESCC Detail Specification No. 9512/002 ISSUE 2 March 2005 esa - = n : w i n ii» = e i s :d Document Custodian: European Space Agency - see https://escies.org


    OCR Scan     		PDF 32/40-BIT PMA18 TSC21020F IRQ30 21020F